Taiwan Semiconductor Manufacturing Comp. Ltd.

Mosaid Technologies Corporation

Kuei-Liang Lu

Ming-Feng Shieh

Chih-Hao Chang

Shao-Ming Yu

Chang-Yun Chang

Yi-Tang Lin

Hsin-Chih Chen

Kai-Tai Chang

Ru-Gun Liu

Ching-Yu Chang

Shih-Ming Chang

Tsai-Sheng Gau

Hung-Chang Hsieh

Chun-Yu Lin

Ya Hui Chang

Ying-Chou Cheng

Yi-Jie Chen

Ya-Hui Chang

Hoi-Tou Ng

Feng-Yuan Chiu

Wen-Chun Huang

Ming-Hui Chih

Chia-Ping Chiang

Wen-Li Cheng

Yu-Po Tang

Wei-De Ho

Ching-Huang Chen

Cheng-Lung Tsai

Ai-Jen Hung

Sheng-Wen Lin

Ho Wei De

Spencer Lin

Irene Ho

A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Structure and method for providing line end extensions for fin-type active regions

A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.

Layout optimization of a main pattern and a cut pattern

A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.

Method for patterning a plurality of features for fin-like field-effect transistor (FinFET) devices

A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.

Photomask and method for fabricating integrated circuit

A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.

Structure and method for transistors with line end extension

Disclosed is a mask for use in a lithography system having a defined resolution. The mask comprises first and second patterns that are greater than the defined resolution and a sub-resolution feature that is less than the defined resolution. Portions of the first and second patterns are positioned close to each other and separated by the sub-resolution feature in an intersection area. The size and shape of the sub-resolution feature are such that when the mask is used in the lithography system, a resulting pattern includes the first and second patterns interconnected with each other through the interconnection area.

Cut-mask patterning process for FIN-like field effect transistor (FINFET) device

A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.

Lithography alignment marks

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.

Method of lithography process with inserting scattering bars

A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.

A method of semiconductor device fabrication including placing a substrate having a first and second features disposed thereon in a vaporizing spray deposition system. An atomizing spray head of the vaporizing spray deposition system is used to deposit a conformal polymer layer on the first and second features. The first feature having the layer of the polymer disposed thereon and having a first width. A spray trim process is performed on the first and second features having the polymer layer disposed thereon using the atomizing spray head.

Method of using a vaporizing spray system to perform a trimming process

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Hsinchu, Taiwan

Kuei-Liang Lu