Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Kuei-Hung Shen

Harry-Hak-Lay Chuang

Hung Cho Wang

Sheng-Huang Huang

Wen-Ting Chu

Yu-Wen Liao

Tong-Chern Ong

Kuo-Yuan Tu

Yung-Hung Wang

Shih-Chang Liu

Cheng-Yuan Tsai

Chern-Yow Hsu

Hsun-Chung Kuang

Ru-Liang Lee

Tien-Wei Chiang

Chien-Chung Hung

Ching-Hsiang Tsai

Shan-Yi Yang

Hsia-Wei Chen

Wei-Chuan Chen

Shy-Jay Lin

Chun-Jung Lin

Wen-Chun You

Kuo-Feng Huang

Meng-Chun Shih

Ching-Huang Wang

Wen-Han Wang

Hung-Cho Wang

Chun-Chi Chen

Keng-Ming Kuo

Bo-Hung Lin

Harry-hak-lay Chuang

Chern-yow Hsu

Sheng-Haung Huang

Cheng-Wei Chien

Chih-Ta Shen

Yuan-Jen Lee

Chang-Hung Chen

Cheng-Tying Yen

Chien-Ming Li

Chia-Yu Wang

Disclosed methods include placing a semiconductor wafer containing MRAM devices into a first magnetic field that has a magnitude sufficient to magnetically polarize MRAM bits and has a substantially uniform field strength and direction over the entire area of the wafer. The method further includes placing the wafer in a second magnetic field having an opposite field direction, a substantially uniform field strength and direction over the entire area of the wafer, and magnitude less than a design threshold for MRAM bit magnetization reversal. The method further includes determining a presence of malfunctioning MRAM bits by determining that such malfunctioning MRAM bits have a magnetic polarization that was reversed due to exposure to the second magnetic field. Malfunctioning MRAM bits may further be characterized by electrically reading data bits, or by using a chip probe to read one or more of voltage, current, resistances, etc., of the MRAM devices.

Magnet configuration systems and methods to detect magnetic tunnel junction coercivity weak bits in MRAM chips

The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.

Memory device

An integrated circuit device includes a substrate, a memory cell, a magnetic shielding element, an interlayer dielectric layer, and a metallization pattern. The memory cell is over the substrate. The memory cell includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element. The magnetic shielding element is around the memory cell. The interlayer dielectric layer surrounds the memory cell and the magnetic shielding element. The metallization pattern is in the interlayer dielectric layer and connected to the top electrode.

Integrated circuit device and method for fabricating the same

The present disclosure provides a semiconductor structure, including an Nmetal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nmetal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)metal layer over the top electrode. The first width is greater than the third width.

Semiconductor structure and method of forming the same

The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.

Semiconductor device including a magnetic tunneling junction (MTJ) device

The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a Nmetal layer, a bottom electrode over the Nmetal layer, a magnetic tunneling junction (MTJ) layer over the bottom electrode, a top electrode over the MTJ layer, and a (N+1)metal layer over the top electrode. The top electrode includes material having an oxidation rate lower than that of Tantalum or Tantalum derivatives. N is an integer greater than or equal to 1.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA) in a dielectric layer, a recap layer on the BEVA, a bottom electrode on the recap layer, and a magnetic tunneling junction (MTJ) layer over the recap layer and vertically aligning with the BEVA. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA and a copper layer over the lining layer, filling the trench of the BEVA. The copper layer has a dimpled structure with a top surface lower than a top surface of the dielectric layer. The recap layer overlaps a top surface of the lining layer, an entire top surface of the copper layer, and a portion of the dielectric stack adjacent to the lining layer.

Semiconductor structure

A storage device includes: a plurality of first magnetic tunnel junction (MTJ) cells disposed on a first portion of a substrate; and a plurality of second MTJ cells disposed on a second portion different from the first portion of the substrate; wherein each of the plurality of first MTJ cells has a first cross-sectional surface area viewing from a top of the substrate, each of the plurality of second MTJ cells has a second cross-sectional surface area viewing from the top of the substrate, and the second cross-sectional surface area is greater than the first cross-sectional surface area.

Storage device having magnetic tunnel junction cells of different sizes, and method of forming storage device

Magnetic memory structure and method of forming the same

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.

The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

Method for testing MRAM device and test apparatus thereof

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a memory region. The memory region comprises a bottom via, a recap layer on the BV, a bottom electrode on the recap layer, a magnetic tunneling junction layer on the bottom electrode, and a top electrode on the MTJ layer. The material of the recap layer is different from that of the BV.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.

Growing community of inventors

Hsinchu, Taiwan

Kuei-Hung Shen