Promos Technologies, Inc

Adesto Technologies Corporation

Mosel Vitelic Corporation

Kuei-Chang Tsai

Chia-Shun Hsiao

Jeffrey Allan Shields

Jin-Ho Kim

Barbara Haselden

Chunchieh Huang

Chakravarthy Gopalan

Daniel Wang

Chunyuan Chao

Yi Ma

Venkatesh P Gopinath

Wei Ti Lee

Chung Wai Leung

Vincent Fortin

George Kovall

Janet Wang

John Ross Jameson, Iii

Janet Siao-Yian Wang

A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.

Memory elements having conductive cap layers and methods therefor

In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.

Resistive switching devices and methods of formation thereof

In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.

Resistive switching devices having a buffer layer and methods of formation thereof

A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.

Method of providing contact via to a surface

Nonvolatile memory wordlines () are formed as sidewall spacers on sidewalls of control gate structures (). Each control gate structure may contain floating and control gates (), or some other elements. Pedestals () are formed adjacent to the control gate structures before the conductive layer () for the wordlines is deposited. The pedestals will facilitate formation of the contact openings () that will be etched in an overlying dielectric () to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Use of pedestals to fabricate contact openings

Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.

Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (X) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask () is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Use of multiple etching steps to reduce lateral etch undercut

A cobalt silicide fabrication process entails first depositing a cobalt layer () on a silicon-containing EPROM region. A titanium layer () is formed over the cobalt layer by ionized physical vapor deposition ('IPVD') to protect the cobalt layer from contaminant gases. Cobalt of the cobalt layer is reacted with silicon of the EPROM region to form a cobalt silicide layer () after which the titanium layer and any unreacted cobalt are removed. Use of IPVD to form the titanium layer by improves the step coverage to produce a better cobalt silicide layer.

Cobalt silicide fabrication using protective titanium

In a nonvolatile memory, a floating gate ( ) is covered with ONO ( ), and a control gate polysilicon layer ( ) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer ( ) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion ( ) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric ( ) is therefore reduced. Other embodiments are also provided.

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Cupertino, CA, United States of America

Kuei-Chang Tsai