Cypress Semiconductor Corporation

Kuantai Yeh

Ahmad Chatila

James Montague Cleeves

Roger F Caldwell

Shahin Sharifzadeh

Daniel J Arnzen

The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

Thin liner layer providing reduced via resistance

The present invention concerns a process that maintains a second (or 'replica') set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or 'replica') alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be 'printed' in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an 'open frame' process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.

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Redwood City, CA, United States of America

Kuantai Yeh