Via Technologies, Inc.

Kuang-Yu Tang

Chun-Yi Wu

Jiing Lin

Hsuan-Yi Wang

The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.

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Taipei, Taiwan

Kuang-Yu Tang