Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuang-Wei Cheng

Chyi-Tsong Ni

Wen-Chih Chiou

Chih-Tsung Lee

Yung-Tsun Liu

Sung-Ju Huang

Cheng-Lung Wu

Shin-Puu Jeng

Der-Chyang Yeh

Shang-Yun Hou

Yuan-Hung Liu

Chun Hua Chang

Chien-Chun Hu

Yi-Fam Shiu

Sheng-Chun Yang

Chen-Hua Douglas Yu

Ku-Feng Yang

Yi-Hsiu Chen

Fang Wen Tsai

Jyh-Shiou Hsu

Jiung Wu

Jiann Sheng Chang

Yi Chou Lai

Wen-Hsun Tsai

The present disclosure relates to systems and methods for reducing the humidity within a FOUP (Front Opening Unified Pod) when loaded on an EFEM (Equipment Front End Module) for transfer of a semiconductor wafer substrate during fabrication processes. A deflector of specified structure is placed inside the EFEM above the load port of the FOUP. The deflector directs airflow in the EFEM away from the load port. The deflector includes a body with a plurality of apertures in the deflector body, and with a sloped front surface. Thus, the degree of penetration of high-humidity air from the EFEM into the FOUP is reduced.

Systems and methods for humidity control of FOUP during semiconductor fabrication

A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.

Heterogenous bonding layers for direct semiconductor bonding

An ultraviolet (UV) lamp assembly of a UV curing tool is provided for curing a low dielectric constant (low-k) material layer of a semiconductor wafer. The UV lamp assembly includes: a UV lamp which emits UV light; a first reflector arranged proximate to a first side of the UV lamp, the first reflector including a first surface facing the UV lamp from which UV light emitted by the UV lamp is at least partially reflected; and a UV reflective coating partially coating the first surface of the reflector. Suitably, a plurality of areas of the first surface of the reflector remain uncoated with the UV reflective coating and the plurality of uncoated areas are arranged to promote a uniform exposure of the semiconductor wafer to UV irradiation.

Reflector and/or method for ultraviolet curing of semiconductor

A method of fabricating a semiconductor device is described. A semiconductor substrate having at least one electrical component is provided. A patterned wiring layer is formed above the semiconductor substrate. The patterned wiring layer includes a plurality of wiring portions, where adjacent of the wiring portions are separated from each other. A first insulating passivation layer is formed over the wiring portions in a region between adjacent wiring portions. The first insulating passivation layer has a horizontal surface in the region between adjacent wiring portions. A second insulating passivation layer is formed on the first insulating passivation layer, wherein the first insulating passivation layer has a side surface which makes an angle with the horizontal surface of greater than 103°.

Semiconductor devices and methods of manufacturing thereof

A method of fabricating semiconductor devices includes: loading one or more semiconductor wafers into a plurality of stations provided within a process chamber; applying a process to the semiconductor wafers which deposits a material on the one or more semiconductor wafers within the process chamber; and cleaning the process chamber. Suitably, cleaning the process chamber includes flowing a cleaning gas into the process chamber toward a deflector arranged in the process chamber, the deflector having a first surface upon which the flowed cleaning gas impinges, the first surface directing a first portion of the flowed cleaning gas impinging thereon in a first trajectory toward a first end of the process chamber and directing a second portion of the flowed cleaning gas impinging thereon in a second trajectory toward a second end of the process chamber, the second end being opposite the first end.

Deflector for chamber cleaning

Methods and systems for chemical vapor deposition (CVD) are disclosed. The methods and systems use a showerhead including a domed internal baffle plate. The domed internal baffle plate is perforated. The presence of the domed internal baffle plate improves the uniformity of gas distribution through the holes of the showerhead across the surface area of the showerhead. This improves deposition uniformity on the semiconducting wafer substrate upon which CVD is being performed, or improves the cleaning of the reaction chamber when a cleaning gas is pumped in through the showerhead.

Device and methods for chemical vapor deposition

A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.

Method and apparatus for semiconductor wafer

A method is provided for supporting environmental control in a semiconductor wafer processing space, the method includes: flowing a first gas under pressure in a first direction through a first diffuser tube, thereby generating a first lateral flow of gas through a sidewall of the first diffuser tube; flowing a second gas under pressure in a second direction through a second diffuser tube, thereby generating a second lateral flow of gas through a sidewall of the second diffuser tube, the second direction being opposite the first direction; combining the first and second lateral flows of gas within a housing; and outputting the combined lateral flows of gas from the housing to produce a laminar gas flow covering an opening to the semiconductor wafer processing space.

Laminar gas flow filter

A diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. A sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. In this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. This may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.

Semiconductor processing tool and methods of operation

A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.

Atomic layer deposition bonding layer for joining two semiconductor devices

A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

Semiconductor processing tool

A semiconductor device may include one or more low dielectric constant (low-κ) layers on a substrate. The semiconductor device may include a dielectric layer on the one or more low-κ layers. The semiconductor device may include a structure through the substrate, the one or more low-κ layers, and the dielectric layer. The semiconductor device may include a liner layer between the structure and the substrate, between the structure and the one or more low-κ layers, and between the structure and the dielectric layer. The semiconductor device may include a capping layer between the liner layer and the dielectric layer and between the liner layer and the one or more low-κ layers.

Growing community of inventors

Hsinchu, Taiwan

Kuang-Wei Cheng