Alpha Omega Semiconductor Inc.

Alpha and Omega Semiconductor (cayman) Ltd.

Kuang Ming Chang

Lin Chen

Zhiye Zhang

Qihong Huang

Allen Chang

Gilbert Lee

Mark Tomas

Zhiqiang Niu

Son Tran

Ning Sun

Tzu-Hsin Lu

A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.

HV converter with reduced EMI

A flyback converter implements a Forced Zero Voltage Switching (ZVS) timing control by detecting a positive current excursion of the secondary winding current as the synchronous rectifier turn off trigger. The synchronous rectifier switch is turned on near the end of the switching cycle or the on duration is extended to develop a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current excursion on the secondary winding current to turn off the synchronous rectifier and to start the next switching cycle. At this point, the voltage across the primary switch has been discharged and the primary switch can be turned on with zero drain-to-source voltage. In other embodiments, zero voltage switching for the off-transition of the primary switch is realized by coupling a capacitor across the primary switch or by coupling a capacitor across the primary winding, or both.

Forced zero voltage switching flyback converter

Zero voltage switching flyback converter for primary switch turn-off transitions

A fault tolerant power supply system includes at least one load switch circuit configured to connect, using a main switch, an input voltage to an output node of the load switch circuit when the load switch circuit is turned on and at least one power channel coupled to the load switch circuit to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is configured to measure a current flowing through the main switch of the load switch circuit, to determine that the current flowing through the main switch of the load switch circuit has exceeded a current limit threshold, and to disable the main switch of the load switch circuit and the low-side power switch of the power channel in response to the determination that the current flowing in the main switch has exceeded the current limit threshold.

Fault tolerant power supply incorporating intelligent load switch to provide uninterrupted power

A fault tolerant power supply system includes at least one load switch configured to connect an input voltage to an output node of the load switch when the load switch is turned on and at least one power channel coupled to the load switch to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is configured to measure a current flowing through the low-side power switch, to determine that the current flowing through the low-side power switch has exceeded a current limit threshold, and to disable the low-side power switch and the load switch in response to the determination that the current flowing in the low-side power switch has exceeded the current limit threshold.

Fault tolerant power supply incorporating intelligent gate driver-switch circuit to provide uninterrupted power

A control circuit for a switching regulator implements constant on-time control scheme with synchronous rectification and applies dual control loops to improve light load efficiency and enhance transient response. In one embodiment, the control circuit includes a first control loop configured to control a one-shot timer to generate a control signal to turn on the main switch when the feedback voltage is below a first reference voltage and a minimum off-time duration has expired. The control circuit further includes a second control loop configured to control the one-shot timer to generate the control signal to turn on the main switch when the feedback voltage is below a second reference voltage and the minimum off-time duration has expired and a low-side current signal has a first state indicative of a light load condition at the output node.

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Fremont, CA, United States of America

Kuang Ming Chang