United Microelectronics Corp.

United Microelectric Corp.

Kuang-Hui Tang

Kai-Kuang Ho

Min-Chih John Hsuan

Kuo-Ming Chen

Chen-Hsiao Wang

Yu-Yuan Huang

Tsung-Kai Yu

A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

Semiconductor device package structure and method for fabricating the same

A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other.

Scribe line structure

A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.

Method for forming crack-stopping structures

Crack-stopping structure and method for forming the same

A package structure is disclosed. The package structure includes a die; a substrate disposed corresponding to the die, wherein the substrate comprises a first dummy pad and a second dummy pad on a first surface of the substrate; and a first solder ball and a second solder ball on a second surface of the substrate and electrically connect the first dummy pad and the second dummy pad respectively.

Method for generating die identification by measuring whether circuit is established in a package structure

A chip packaging process includes providing a wafer, having an active surface and a backside. The wafer has a first chip area and a second chip area adjacent to the first chip area. The wafer has several first and second bond pads on the active surface in the first and second chip areas respectively. Several through holes are formed on the wafer. The through holes pass through the wafer and connect the active surface and the backside. The through. holes are arranged between the first chip area and the second chip area. Several connecting lines are formed on peripheral surfaces of the through holes. Each of the connecting lines has a first end portion extending on the active surface and a second portion extending on the backside. Each the first end portion is electrically connected to one of the first bond pads and one of the second bond pads.

Growing community of inventors

Kaohsiung, Taiwan

Kuang-Hui Tang