Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Epistar Corporation

Kuang-Huan Hsu

Ching-Wen Hsiao

Chyi Shyuan Chern

Hsin-Hsien Wu

Chun-Jung Huang

Yung-Lin Hsu

Chun-Lin Louis Chang

Span Lu

Chih-Wei Hsu

Hsu-Shui Liu

Wei-Chih Chen

Chih-Wei Chen

Han-Wen Liao

Jen-Ti Wang

Yung-Chang Chen

Ren-Chyi You

Shui-Tien Lin

Fu-Wen Liu

Chih-Hung Liu

Yu-Yao Huang

Chen-Yung Lin

Liang-Kai Huang

Hsiao-Wei Chen

A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

Semiconductor structure and planarization method thereof

A fault detection method in a semiconductor fabricating factory is provided. The method includes delivering a test vehicle along a rail to a test region. The method further includes projecting a test signal from a transducer that is positioned on the test vehicle over a check board when the test vehicle is located within the test region. The check board and the test vehicle are arranged along an axis that is parallel to the rail. The method also includes performing an analysis of the test signal projected over the check board. In addition, the method includes issuing a warning alarm when an abnormality is detected based on the analysis result.

Fault detection method in semiconductor fabrication

Disclosed is a method and a system for monitoring of environment and security in a fabrication facility. In one embodiment, a method comprising: transporting an automated material handling system (AMHS) vehicle from a first position to a second position; and detecting at least one parameter using at least one sensor located on the AMHS vehicle to determine at least one environmental or security condition between the first and second positions.

Intelligent environmental and security monitoring system

A device includes: a substrate; and a doped III-V compound layer disposed over the substrate; wherein: the doped III-V compound layer includes an upper boundary; the upper boundary has a micro-roughened texture and a macro-roughened texture where the micro-roughened texture located on; and the upper boundary includes dopant ions that are not present in a remainder of the doped III-V compound layer underneath the upper boundary.

Light emitting diode

A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process.

Light emitting diode and method of fabrication thereof

An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.

Methods of fabricating light emitting diode devices

Provided are a system and method for preventing contamination in a semiconductor manufacturing environment. The method includes comparing one or more attributes associated with a product, such as a substrate, with one or more attributes associated with an operation. If the comparison indicates that the product is not compatible with the operation, then the operation is suspended with respect to the product. If the comparison indicates that the product is compatible with the operation, then the operation is performed on the product.

System and method for process contamination prevention for semiconductor manufacturing

An algorithm can be performed to control the dispatch of products in a fabrication or manufacturing facility. The queue time constraint tolerances and tool throughput are initialized for each product. Next the multiple processing demand time can be calculated for each product. The aggregating queue time constraint can then be calculated for each product. If the multiple processing demand time is less than the aggregating queue time constraint for each queue time limit tool, then any lot can be selected to be processed. Otherwise, the product at the given tool should be further processed.

Method for controlling queue time constraints in a fabrication facility

Within both a system and a method for managing within a fabrication facility a work-in-process (WIP) workload within the fabrication facility there is first provided a fabrication facility comprising: (1) a plurality of fabrication tools which perform an equivalent fabrication function; and (2) at least one quantity of existing work-in-process (WIP) workload which requires multiple sequential processing within only one fabrication tool within the plurality of fabrication tools which perform the equivalent fabrication function. There is then determined for the plurality of fabrication tools a plurality of tool loading coefficients which take into consideration complete processing of the at least one quantity of work-in-process (WIP) workload which requires multiple sequential processing within the only one fabrication tool within the plurality of fabrication tools. There is then introduced into the fabrication facility a quantity of new work-in-process (WIP) workload which also requires multiple sequential processing within only one fabrication tool within the plurality of fabrication tools which performs the equivalent fabrication function, wherein the quantity of new work-in-process (WIP) workload is allocated to a fabrication tool within the plurality of fabrication tools having a most favorable tool loading coefficient within the plurality of tool loading coefficients.

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Hsinchu, Taiwan

Kuang-Huan Hsu