Advanced Semiconductor Engineering, Inc.

Kuang-Hsiung Chen

Sheng-Ming Wang

Yu-Ying Lee

Tien-Szu Chen

Yuan-Chang Su

Shih-Fu Huang

Bernd Karl Appelt

Chia-Cheng Chen

Pao-Ming Hsieh

Lu-Ming Lai

Hsun-Wei Chan

Wun-Jheng Syu

Tzu-Hui Chen

Ying-Chung Chen

Hsiang-Ming Feng

Chih-Hung Hsu

Ming Chiang Lee

Mei-Lin Hsieh

Chia-Hsiung Hsieh

I-Cheng Wang

Yu-Tzu Peng

You-Lung Yen

Chun-Che Lee

Yu-Hsuan Tsai

Yi-Cheng Hsu

Yu-Ching Sun

Fa-Hao Wu

Bing-Yun Cheng

Ren-Yi Cheng

Pei-Yu Hsu

Chih-Cheng Lee

Chi-Tsung Chiu

Hsin-Ying Ho

Ming-Chiang Lee

Chi-Chih Shen

Jen-Chuan Chen

Shih-Chieh Tang

Wen-Hsiung Chang

Li-Chuan Tsai

Chi-Chih Chu

Hui-Shan Chang

Yu-Shun Hsieh

Cheng-Yi Weng

Kay Stephan Essig

Ta-Chun Lee

Yuan-Chun Chen

Yen-Hua Kuo

Ko-Pu Wu

Yi Wen Chiang

Yueh-Chen Hsu

Tsai Wan

Chen-Yu Chia

Ya-Wen Hsu

Shing-Cheng Liang

Chen-Ming Cheng

Hung-Ju Chung

Chun-Hung Hsu

An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

Optical module and method of making the same

A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.

Substrate structure, semiconductor package structure and method for manufacturing semiconductor package structure

A semiconductor device package includes a carrier, a die, an encapsulation layer and a thickness controlling component. The die is disposed on the carrier, wherein the die includes a first surface. The encapsulation layer is disposed on the carrier, and encapsulates a portion of the first surface of the die. The encapsulation layer defines a space exposing another portion of the first surface of the die. The thickness controlling component is disposed in the space.

Semiconductor device package and method for manufacturing the same

A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.

Device including a plurality of leads surrounding a die paddle and method for manufacturing the same

A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.

Substrate, semiconductor package thereof and process of making same

A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.

Semiconductor package device having glass transition temperature greater than binding layer temperature

A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.

Semiconductor package and method of manufacturing the same

A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.

Semiconductor device package and method of manufacturing the same

The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

Substrate having a conductive structure within photo-sensitive resin

An optical module includes a carrier, a light source disposed on an upper side of the carrier, an optical sensor disposed on the upper side of the carrier, and a housing disposed on the upper side of the carrier over the light source and the optical sensor. The housing defines a first aperture exposing at least a portion of the light source and a second aperture exposing at least a portion of the optical sensor. An outer sidewall of the housing includes at least one singulation portion adjacent to the upper side of the carrier and perpendicular to the upper side of the carrier.

A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

Semiconductor device package with a conductive post

In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).

A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.

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Kaohsiung, Taiwan

Kuang-Hsiung Chen