Macronix International Co., Ltd.

Hon Hai Precision Industry Co., Ltd.

Hon Young Semiconductor Corporation

Kuang-Hao Chiang

Erh-Kun Lai

Dai-Ying Lee

Shang-Yu Chuang

Hao-chung Kuo

Ming-Hsiu Lee

Yu-Hsuan Lin

Feng-Min Lee

Yu-Yu Lin

Chun-Min Cheng

Kuo-bin Hong

Yi-Kai Hsiao

A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

Manufacturing method of a semiconductor device with junction field effect transistor

An infrared sensor includes a substrate, an active pixel array, a reference pixel array, a light absorbing layer, a sidewall spacer, and a shading layer. The active pixel array is over the substrate. The reference pixel is over the substrate, adjacent to the active pixel array, and having a reference pixel. The reference pixel includes a platform, a resistor, and an infrared sensing material layer. The resistor is on the platform. The infrared sensing material layer is over the resistor. The light absorbing layer is over the reference pixel. The sidewall spacer is over the reference pixel and extends along a sidewall of the light absorbing layer. The shading layer is conformally formed over the light absorbing layer and the sidewall spacer.

Infrared sensor

The present disclosure provides a bolometer including a substrate, a reflecting mirror on the substrate, and a temperature sensing unit above the reflecting mirror. The temperature sensing unit includes a first insulating layer, a thermistor on the first insulating layer, a second insulating layer on the thermistor, an electrode layer in the second insulating layer and right above the thermistor, and a metal meta-surface in the second insulating layer and right above the electrode layer. The electrode layer includes a plurality of electrodes separated from each other. A projection region of the metal meta-surface on the thermistor is equal to or larger than the thermistor.

Bolometer and manufacturing method of temperature sensing unit

A manufacturing method of a semiconductor structure includes the following operations. A stacked structure is formed on a substrate. The stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which the sacrificial layers include germanium, and germanium concentrations of the sacrificial layers decrease from bottom to top. A dummy gate structure is formed on the stacked structure. A spacer is formed on both sides of the dummy gate structure. The dummy gate structure is removed, thereby forming an opening. The sacrificial layers are removed from the opening. A gate structure is formed to cover the semiconductor layers. In another manufacturing method, the stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which thicknesses of the semiconductor layers increase from bottom to top, or thicknesses of the sacrificial layers increase from bottom to top.

Manufacturing method of semiconductor structure

A floating bridge structure includes a substrate, a floating bridge layer, and at least one support. The floating bridge layer is on the substrate and substantially parallel to an upper surface of the substrate. The support extends on a vertical surface from the substrate to the floating bridge layer, in which the vertical surface is substantially perpendicular to the upper surface of the substrate.

Floating bridge structure and infrared sensing device

A method for controlling accumulated resistance property of a ReRAM device, wherein the method includes steps as follows: A first programing pulse set is firstly applied to a ReRAM device for acquiring a reference accumulated resistance distribution. A second programing pulse set is then provided according to the reference accumulated resistance distribution, and the second programing pulse set is applied to the ReRAM device, to make the ReRAM device having a predetermined accumulated resistance distribution.

Method for controlling accumulated resistance property of ReRAM device

A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.

Three dimensional memory device and method for fabricating the same

A memory device includes a memory unit and a selector. The memory unit is configured to store data. The selector is coupled to the memory unit, and has a variable electrical parameter capable of being set to different levels. When the variable electrical parameter of the selector is set to a first level, the selector is turned on in response to an operation signal that is enabled, allowing the data stored in the memory unit to be accessed; when the variable electrical parameter of the selector is set to a second level, the selector remains turned off when receiving the operation signal that is enabled, prohibiting the data stored in the memory unit from being accessed.

Memory device, system and operating method thereof

A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom oxide layer, a first insulation recess, a plurality of insulating layers on the first conductive layer, a plurality of second conductive layers, a second insulation recess, a channel layer on a sidewall of the second insulation recess, and a memory layer located between the channel layer and the second conductive layers. The first insulation recess has a first width and penetrates through the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess located on the first insulation recess has a second width larger than the first width and penetrates through the insulating layers and the second conductive layers.

Memory structure and manufacturing method of the same

A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

Semiconductor device and manufacturing method thereof

A method for forming a semiconductor structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a buffer layer on a buried layer. Next, a first opening is formed through the stack and through a portion of the buffer layer. Thereafter, a spacer is formed on a sidewall of the first opening.

Method for forming a semiconductor structure

A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

Resistive memory device with ring-shaped metal oxide on top surfaces of ring-shaped metal layer and barrier layer

A memory device includes a first metal layer and a second metal layer, a metal oxide layer disposed between the first metal layer and the second metal layer, and at least one oxygen control layer disposed between the metal oxide layer and at least one of the first metal layer and the second metal layer. The at least one oxygen control layer has a graded oxygen content.

Growing community of inventors

Taoyuan, Taiwan

Kuang-Hao Chiang