Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuang-Ching Chang

Hui-Zhong Zhuang

Jung-Chan Yang

Chih-Liang Chen

Kuo-Nan Yang

Ting-Wei Chiang

Shang-Hsuan Chiu

Chi-Yu Lu

Jerry Chang Jui Kao

Tzu-Ying Lin

Jia-Hong Gao

I-Wen Wang

Yueh Chiang

Ming-Xiang Lu

Po-Chih Cheng

An integrated circuit includes a first power rail on a back-side of a wafer and being configured to supply a first voltage, a header circuit coupled to the first power rail and being configured to supply the first voltage to the first power rail, a second and third power rail on the back-side of the wafer, a fourth power rail on a front-side of the wafer, and a fifth power rail on the back-side of the wafer. The second and third power rail being configured to supply a second voltage. The fourth power rail includes a first set of conductors configured to supply a third voltage to the header circuit. The fifth power rail is configured to supply the third voltage and is separated from the first power rail in a first and second direction, and is separated from the second and third power rail in the first direction.

Integrated circuit and method of forming the same

An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.

Flip-flops having strong transistors and weak transistors

An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.

A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Base layout cell

An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.

An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.

A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments.

Method for improved cut metal patterning

A method of preparing an integrated circuit device design including analyzing a preliminary device layout to identify a vertical abutment between a first cell and a second cell, the locations of, and spacing between, internal metal cuts within the first and second cells, indexing the second cell relative to the first cell by N CPP to define one or more intermediate device layouts to define a modified device layout with improved internal metal cut spacing in order to suppress BGE and LE.

Growing community of inventors

Hsinchu, Taiwan

Kuang-Ching Chang