Macronix International Co., Ltd.

Mosel Vitelic Corporation

Industrial Technology Research Institute

Other

Kuang-Chao Chen

Tuung Luoh

Ling-Wuu Yang

Chin-Ta Su

Ta-Hung Yang

Tuby Tu

Ta-Hone Yang

Shaw-Tzeng Hsia

Hsueh-Hao Shih

Yung-Tai Hung

Shing-Ann Luo

Yuan-Chieh Chiu

Tahone Yang

Chi-Tung Huang

Ling-Wu Yang

Chin-Tsan Yeh

Hsiang-Chou Liao

Sheng-Hui Hsieh

Shih-Ping Hong

Kuang-Wen Liu

Chi-Pin Lu

Ting-Feng Liao

Chun Chiang

Yen-Ju Chen

Jui-Lin Lu

Yao-An Chung

Nan-Tsu Lian

Chi-Min Chen

Ming-Da Cheng

Chien-Hung Zordius Chen

Hong-Ji Lee

An Chyi Wei

Chia-Wei Wu

Wen-Doe Su

Chun-Fu Chen

Pei-Ci Jhang

Chao-Lung Lo

I-Jen Huang

Yi-Fu Chung

Chien-Hung Lu

Tien-Chu Yang

Ling Wuu Yang

Che-Lun Hung

Yuhturng Liu

Danny Wu

Kent Liao

Dinos Huang

ChungTe Hsuan

Ming Da Cheng

Masaru Nakamichi

Wen-Ming Chang

Yukai Huang

Chun-Ming Cheng

Chun Min Cheng

Chien Hung Chen

Ricky Huang

Candy Jiang

Chih-Hsien Lo

Hsing-Hua Chiu

Donald Huang

May Wang

Chin Hsiang Lin

Chin-Wei Liao

Sheng-Yuan Chang

Sheng Hui Hsieh

Sung Kun-Yu

An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.

Memory device with multi-layered charge storage stack

A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Method for fabricating memory device

A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Memory device and method for fabricating the same

Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Word line structure and method of manufacturing the same

Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Method of fabricating semiconductor device

A semiconductor substrate and a semiconductor device are provided in which the substrate includes a plurality of chips. Each of the chips includes at least one array region and at least one periphery region. The semiconductor substrate has a plurality of trenches disposed in the array region and/or the periphery region, wherein a ratio of the depth of the trenches to the thickness of the semiconductor substrate is between 0.001 and 0.008, and the area of all the trenches is between 5% and 90% based on the total area of the semiconductor substrate.

Semiconductor substrate and semiconductor device

An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Integrated circuit device with layered trench conductors

Semiconductor device and method of fabricating the same

A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

Method and system for detecting defects of wafer by wafer sort

A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Method for measuring and analyzing surface structure of chip or wafer

Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and conductive layers over a substrate, identifying a plurality of bit line locations and word line locations for the initial stack, including a first bit line location and a first word line location, and forming, from the initial stack, a vertical arrangement of bit lines in the first bit line location, the vertical arrangement of bit lines having opposing sidewalls. The method further comprises forming a word line by forming a thin conductive layer over selected sections of the opposing sidewalls, the selected sections of the opposing sidewalls being sections within the first word line location. The forming the word line further comprises depositing conductive material adjacent to each thin conductive layer, the deposited conductive material in direct contact with the thin conductive layer.

Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices

A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal.

Method for detecting an electrical defect of contact/via plugs

An electron beam (E beam) inspection optimization is provided, in which a plurality of initial inspection regions in a chip are obtained, wherein a center of each of the initial inspection regions is a defect point. Thereafter, reset inspection regions are regenerated without overlap, wherein each of the reset inspection regions is within a scope covered by a field of view (FOV) and the scope contains at least one of the defect points. Afterwards, a center of the reset inspection region is transferred into an inspection center, and then an E beam inspection is performed on the inspection center.

Electron beam inspection optimization

A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

Method of detecting bitmap failure associated with physical coordinate

Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.

Method for fabricating conductive lines of a semiconductor device

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Hsinchu, Taiwan

Kuang-Chao Chen