Intel Corporation

Kuan Zhou

Bryan K Casper

Aaron K Martin

Ganesh Balamurugan

Frank Patrick O'Mahony

Mozhgan Mansuri

Navneet Dour

Roger K Cheng

Ajay Balankutty

Alex Thomas

Sridhar Tirumalai

Krishnamurthy Venkataramana

Hari Venkatramani

Quoc Nguyen

Bruce Querbach

Li Pan

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)

An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.

Low power and area efficient memory receiver

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Portland, OR, United States of America

Kuan Zhou