Intel Corporation

Kuan-Yueh Shen

Rachael Jade Parker

Nasser A Kurd

Yongping Fan

David Johnston

John Fallin

Gennady Goltman

Javier Dacuna Santos

Tahir Ghani

Anand S Murthy

Annalisa Cappellani

Atul Maheshwari

Harry Gomez

Stephen M Ramey

Parker J Rachel

Jae Limb

An apparatus has a phase lock loop with an adaptive loop filter that has a reset circuit controlled by a power gating pulse circuit.

Phase lock loop with an adaptive loop filter

Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

Monitor circuitry for power management and transistor aging tracking

A multi-feedback circuit that compares a duty cycle corrected reference clock f, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fwith approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

Low power apparatus and method to multiply frequency of a clock

The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a first read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.

Method, system and apparatus for error correction coding embedded in physically unclonable function arrays

The bandgap-less apparatus is a fast settling circuit (e.g., with settling time of less than 40 ns) that can leverage proportional-to-absolute-temperature only (PTAT-only) currents to generate a zero or substantially zero temperature coefficient, or even complementary-to-absolute-temperature (CTAT), reference current or voltage, without the need of a native CTAT component or bandgap diodes. The apparatus subtracts two different PTAT currents so that the resulting current is zero-TC. The resulting current is a reference current. The resulting current can be converted to a reference voltage.

Bandgap-less reference generator

An apparatus is provided which comprises: a phase detector to receive a reference clock and a feedback clock; and one or more switchable heat elements controllable by an output of the phase detector, wherein the one or more switchable heat elements are coupled to a physically unclonable function circuit.

Supply voltage and temperature insensitive physically unclonable function circuit

Techniques and mechanisms for changing a consistency with which a cell circuit ('cell') settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCl) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCl stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

Device, system, and method to change a consistency of behavior by a cell circuit

An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.

Apparatus and method for generating stable reference current

Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

Phase-locked loop with lower power charge pump

Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.

Frequency control system with dual-input bias generator to separately receive management and operational controls

Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

Apparatus to reduce power of a charge pump

A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (H), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hproximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

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Portland, OR, United States of America

Kuan-Yueh Shen