Sun Microsystems, Inc.

Kuan-yu J Lin

Song C Kim

An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node. As such, the precharge FET is controlled and the dynamic node is properly precharged independent of the RESET pulse width.

Method of charging a dynamic node

Apparatus and method for resetting a dynamic logic circuit

A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block. A subsequent rising edge of a delayed version of the clock signal is employed by a reset unit to generate a precharge signal which charges the evaluate and evaluate complement signal back to their precharge logic state. The data out and data out complement signals are correspondingly discharged, producing the falling edge of the output pulse and terminating assertion of the precharge signal. The dynamic pulse register is thus able to generate a pulse output in a single logic stage employing a standard clock signal. The speed of the pulse register may be advantageously increased without introducing the complexity of an early clock signal.

Method for generating a pulse output in a dynamic register

Dynamic pulse register with scan functionality

A memory circuit which steers read/write data to a memory array including a plurality of columns (at least one of which is redundant). Coupled to the bit line of each column are a normal mode write transistor and a redundant mode write transistor. If a failing column is detected during manufacturing testing of the memory array, a repair signal for each of the failing column and subsequent columns in the array are de-asserted. When a write operation is performed on the array, an input data bit is provided corresponding to each non-redundant column in the array. The input data bit written to a particular bit line, however, depends upon the state of the repair signal for that column. If the repair signal for a particular column is asserted, the input to the normal mode write transistor is conveyed as write data. Conversely, the input to the redundant mode write transistor is conveyed as write data if the repair signal is de-asserted for a particular column. Similar circuitry is also included to perform steering during a read operation. By proper assertion of the repair signal for each column, the memory circuit causes failing columns to be bypassed during operation of the memory array. The configuration of this memory circuit may advantageously increase the speed of the array for read/write operations. In addition, the loading on each bit line may be decreased, which advantageously decreases write recovery time for the array.

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Mountain View, CA, United States of America

Kuan-yu J Lin