Acer Inc.

Pfc Device Holdings Limited

United Microelectronics Corp.

Getac Technology Corporation

Everlight Electronics Co., Ltd.

Brilliant Sensing Technology

Kuan-Yu Chen

Shu-Chun Liao

Ching-Ho Tsai

Chiu-Te Lee

Mei-Ling Chen

Chiu-Ling Lee

Tseng-Hsun Liu

Chih-Chung Wang

Min-Hsuan Tsai

Wen Chun Wang

Wei-Lin Chen

Yao-Wei Yang

Kuan-Jung Chen

Hsueh-Mao Cheng

Shin-Pang Yang

Te-Chang Chiu

A detecting circuit of an external display device includes a first connector, a display circuit configured to provide a display signal to the external display device through the first connector, a switch circuit, a power supply circuit configured to provide power needed for operating the display circuit through the switch circuit when the switch circuit is on, and a control circuit configured to turn on the switch circuit upon detecting the external display device so as to connect the power supply circuit to the display circuit. When the switch circuit is on, the control circuit accumulates a duration or a number of times of detection that the external display device is continually not detected, and then turns off the switch circuit to disconnect the power circuit from the display circuit when the duration reaches a time threshold or the number of times of detection reaches a count threshold.

Detecting circuit and detecting method of external display device

A semiconductor device with super junction and process for the same is disclosed. The semiconductor device includes a silicon substrate and a first conductive type epitaxial layer thereon, a plurality of second conductive type conductive pillars formed below an upper face of the first conductive type epitaxial layer, where the second conductive type conductive pillars are implanted with neutral element having predetermined amount. When the semiconductor device operates in a predetermined temperature, the releasing amount of the neutral element can completely or partially compensate the releasing amount of carrier of opposite polarity from the epitaxial layer for the second conductive type conductive pillars due to the predetermined temperature, thus prevent the degrade of endurance ability for the surge voltage.

Semiconductor device with super junction and process for the same

A maintenance method for network connection and a computer system are provided. The method is adapted to a computer system having a real-time clock. The real-time clock is configured to regularly wake up the computer system to check whether a network connection is working normally. In the method, a wake up operation to wake up the computer system is received from a user. It is determined whether a connection time of maintaining the network connection so far from a last time of entering a power saving mode is greater than a counting time for the real-time clock to wake up the computer system. It is tested whether the network connection is working normally when the connection time is greater than the counting time. The counting time of the real-time clock is updated to the connection time when the network connection is working normally.

Maintenance method for network connection and computer system

An electronic apparatus having an input unit and a network card and a wake-up method thereof are provided. In the method, an input event triggered by the input unit is received. Next, whether the electronic apparatus is in a partial wake-up mode entered after being woken up by the network card is determined. Then, the electronic apparatus is woken up to a normal operation mode if the electronic apparatus is in the partial wake-up mode.

Electronic apparatus and wake-up method thereof

A low-temperature epitaxial method manufactures backside field stop layer of insulated gate bipolar transistor (IGBT) first provides a first conductive type substrate and fabricates front-side elements and front metal layer on a front side of the IGBT. A second conductive type impurity layer is formed on a back side of the first conductive type substrate by low-temperature epitaxial process and a collector metal layer is formed on bottom face of the first conductive type substrate.

Low-temperature epitaxial method for manufacturing backside field stop layer of insulated gate bipolar transistor (IGBT)

A low-temperature oxide method is used for manufacturing backside field stop layer of IGBT and first fabricates front elements and front metal layer on a first face of a first conductive type substrate. A multiple-recesses structure is formed on a back side of the first conductive type substrate. Each of the recess in the multiple-recesses structure has first conductive type implanted patterns on exterior sides thereof and the multiple-recesses structure has a first conductive type implanted layer on bottom thereof. A plurality of first conductive type polysilicon layers are deposited into the multiple-recesses structure and respectively corresponding to the first conductive type implanted patterns. A second conductive type impurity layer is formed on the bottom of the first conductive type substrate and laser annealing is conducted to form backside field stop layer for IGBT.

Low-temperature oxide method for manufacturing backside field stop layer of insulated gate bipolar transistor

Disclosed is an apparatus for pesticide detection in aqueous solution was provided, wherein an electrochemical biosensor, a container for mixing and an electrical signal analyzer were used, and the biosensor is disposable.

Apparatus for residual pesticide detection

The present invention provides a semiconductor device structure which integrates a lateral diffused metal oxide semiconductor (LDMOS) with a Schottky diode, including: a substrate, having a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region having a second conductivity type complementary to the first conductivity type, a source region formed in the substrate, the source region having the second conductivity type, a high-voltage well region formed in the substrate, the high-voltage well region having a first conductivity type; a Schottky diode disposed on the substrate and disposed beside the LDMOS, wherein the semiconductor device structure is an asymmetric structure, and a deep well region disposed in the substrate and having the second conductivity type, wherein the LDMOS and the Schottky diode are all formed within the deep well region.

High voltage semiconductor devices with Schottky diodes

A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

High voltage metal-oxide-semiconductor transistor device and manufacturing method thereof

A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block.

Growing community of inventors

Taipei, Taiwan

Kuan-Yu Chen