Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Faraday Technology Corporation

Other

Lite-on Technology Corporation

Getac Technology Corporation

Lite-on Electronics (guangzhou) Limited

Tsinghua University

Amtran Technology Co., Ltd.

Mediatek Corporation

Compal Electronics, Inc.

Institute for Information Industry

Everlight Electronics Co., Ltd.

Macroblock, Inc.

National Yang Ming Chiao Tung University

Kuan-Yu Chen

Hsueh-Chang Sung

Hsien-Hsin Lin

Tsz-Mei Kwok

Chien-Chang Su

Yi-Fang Pai

Wen-Ching Hsiung

Chia-Liang Lai

Wei-Cheng Lin

Yuan-Hsun Chang

Ting-Chun Huang

Chun Huan Wei

Pin Yu Hsu

Szu-Yuan Chen

Po-June Chen

Jeng-Dau Chang

Ming-Hua Yu

Weng Chang

Seok-Lyul Lee

Chun-Feng Nieh

Ming-Hsien Lee

Yu-Feng Chien

Yi-Suei Liao

Yung-Chang Chen

Chien-Yu Yi

Ann-Shyn Chiang

Chia-En Wu

Huang-Pin Lin

Hsiu-Ming Chang

Chi-Han Yang

Chien-Cheng Lin

Wei-Chia Chiu

Lung-Hui Chen

Kuo-Liang Shen

Hsiao-Lung Lin

Feng-Shou Lin

Jian-Lin Chen

Yi-An Chien

Hung-Tsai Weng

Che-Cheng Chang

Jiann-Tyng Tzeng

Shih-Wei Peng

Kun-Mu Li

Chih-Wei Chen

Wen-Hao Hsu

Chun-Fai Cheng

Chun-Hsin Liu

Tien-Lun Ting

Yu-Ting Huang

Chien-Liang Chen

Pei-Kuei Tsung

Chih-hao Hsu

Hung-Jen Chen

Hung-Min Shih

Jiun-Haw Lee

Wei-Cheng Cheng

Ching-Ian Chao

Kuo-Hui Chang

Chun-Kuei Wen

Ming-Shih Yu

Kuan-Ta Chen

Yao-Chi Peng

Wai-Kei Mak

Chia-Shin Weng

Ming-Hung Chien

Hao-Chieh Lee

Shi-Hao Li

Chun-Hsien Yeh

Mao-Kuo Wei

Jih-Houng Lee

Sheng-hsiung Chen

Ting-Chi Wang

Chien-Chun Chen

Chen-Lun Chiu

Min-Yu Wang

Fung Ka Hing

Yen-Yin Huang

Ting-Ta Chiang

Wei-cheng Tzeng

Kun-Yi Lee

Cheng-Lung Jen

Pao-Yu Huang

Yuan-Min Hu

Wei-Yu Lee

Huang-Chuan Chen

Ta-Shun Lin

Ta-Yi Chien

Kuan-Chung Chen

Cheng-Hui Lin

Chun-Hung Wu

Chia-Yang Cheng

Yen-Juei Lin

Chin-Yu Chang

Yi-Chun Huang

Chauo-Min Chen

Fen-Ling Hu

Hsuan-Han Liang

Hoang-Yan Lin

Feng-Yi Yu

Chien-Hsun Kao

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

APR placement for hybrid sheet cells

A wireless signal receiving device and system are provided. The wireless signal receiving system includes a wireless signal receiving device and a Global Position System (GPS) module. The wireless signal receiving device includes an antenna for receiving first wireless signals in a plurality of frequency bands, a first filter coupled to the antenna for splitting the first wireless signals in the plurality of frequency bands into wireless signals in different frequency bands, and a second filter coupled to the first filter for compositing the wireless signals in the different frequency bands into second wireless signals having a plurality of frequency bands. The GPS module is coupled to the wireless signal receiving device. The GPS module is for receiving the second wireless signals having the plurality of frequency bands.

Wireless signal receiving device and system

A method includes etching a trench in a substrate adjacent to a gate structure, wherein the trench includes a bottom surface and a tip portion extending under a spacer of the gate structure. The method further includes epitaxially growing a first semiconductor material in the trench, wherein the first semiconductor material covers an entirety of the bottom surface of the trench, and the first semiconductor material grows in the tip portion. The method further includes epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material, the second semiconductor material covers the first semiconductor material, and the second semiconductor material directly contacts the substrate between the bottom surface of the trench and the tip portion.

Method of forming devices with strained source/drain structures

A wireless signal receiving circuit includes: an antenna structure, for receiving a wireless reception signal in a plurality of frequency bands; a first diplexer, connected to the antenna structure, for splitting the wireless reception signal into a first wireless signal in a low frequency band and a second wireless signal in a high frequency band; a first extractor, coupled to the first diplexer, for receiving the first wireless signal and splitting the first wireless signal into a third wireless signal and a fourth wireless signal; a second diplexer, coupled to the antenna structure and connected to the first extractor, for combining the wireless reception signal and the third wireless signal into a fifth wireless signal; and a third diplexer, coupled to the first extractor and the first diplexer, for combining the second wireless signal and the fourth wireless signal into a sixth wireless signal.

Wireless signal receiving circuit and system

Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process. In one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.

MIM structure

A protecting method for preventing solder crack failure in an electronic product is provided. Firstly, a step (a) is performed to confirm that a crack incidence rate of a metallic solder material in a printed circuit board is high. In a step (b), a protecting mechanism of controlling the electronic product to enter an idle mode and leave the idle mode is activated. Consequently, an operating temperature of the electronic product decreases at a first average drop rate.

Protecting method for preventing solder crack failure in electronic product

A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

Metal-insulator-metal capacitor within metallization structure

A wireless signal receiving device and system are provided. The wireless signal receiving device includes: a plurality of antennas for receiving a first wireless signal, a second wireless signal and an external antenna wireless signal; a first signal splitting device for splitting the external antenna wireless signal into a third wireless signal and a fourth wireless signal in different frequency bands; a first signal switching device for individually switching and outputting wireless signals; a second signal switching device for individually switching and outputting wireless signals; a first module switching device for switching output routes of wireless signals; a second module switching device for switching output routes of wireless signals; and a first signal combination device for combining wireless signals into a fifth wireless signal.

The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

Method, non-transitory computer-readable medium, and apparatus for arranging electrical components within a semiconductor device

A catalyst is illustrated, which has 70-90 parts by weight of mica, 1-10 parts by weight of zeolite, 5-15 parts by weight of titanium dioxide, 1-10 parts by weight of aluminum oxide, 1-5 parts by weight of sodium oxide and 1-5 parts by weight of potassium oxide. The present disclosure also illustrates a pyrolysis device using the catalyst, and further illustrates a pyrolysis method using the catalyst and/or the pyrolysis device for thermally cracking an organic polymer.

Catalyst, pyrolysis device and pyrolysis method

An electronic device includes a communication module, an external module and a signal integration circuit. The signal integration circuit includes a first input port, a second input port, a third input port and an output port. The first input port is for inputting an input signal. The second input port is for selectively inputting a first L1 band signal. The third input port is for selectively inputting a second L1 band signal. The output port selectively outputs a first output signal or a second output signal. When the third input port is coupled to an external module, the third input port is for inputting the second L1 band signal, and the output port outputs the second output signal. When the third input port is not coupled to the external module, the second input port is for inputting the first L1 band signal, and the output port outputs the first output signal.

Signal integration circuit and electronic device

A light-emitting device including a substrate, an insulating layer, an inner circuit structure, a plurality of light-emitting elements, an insulating encapsulation layer, and a transparent conductive layer is provided. The insulating layer is disposed on the substrate. The inner circuit structure is disposed on the insulating layer. The light-emitting elements are correspondingly disposed on the inner circuit structure. The insulating encapsulation layer is disposed on the inner circuit structure. The insulating encapsulating layer covers a portion of the inner circuit structure and encapsulates the light-emitting elements. The transparent conductive layer is disposed on the insulating encapsulating layer. The transparent conductive layer electrically connects the light-emitting elements, and serially connects the light-emitting elements.

Light-emitting device

A pixel driving device includes a capacitance, a reset circuit, a compensation circuit, a driving transistor and a first transistor. Reset circuit and compensation circuit are coupled to a first end and a second end of capacitance. First transistor is coupled between second end of driving transistor and second end of capacitance. Reset circuit resets first end of capacitance at a power supply voltage and reset second end of capacitance at a reference voltage according to a first sweep signal respectively. Compensation circuit writes a data voltage into first end of capacitance via driving transistor and second end of capacitance is maintained at reference voltage according to a second sweep signal. First transistor generates a driving voltage difference between first end and second end of capacitance according to a control signal. Driving transistor outputs a current to a luminous element according to driving voltage difference.

Pixel driving device and method for driving pixel

A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (S/D) features in the substrate. At least one of the S/D features is located in a trench. The at least one S/D feature includes a first semiconductor material covering an entirety of a bottom surface of the trench. The at least one S/D feature further includes a second semiconductor material over the first semiconductor material. The at least one S/D feature further includes a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions directly contacting the substrate. The second semiconductor material surrounds the third semiconductor material. In some embodiments, the physically discontinuous portions of the first semiconductor material include tip portions within tips of the trench.

Devices with strained source/drain structures and method of forming the same

Growing community of inventors

Taipei, Taiwan

Kuan-Yu Chen