United Microelectronics Corp.

National Cheng-kung University

Kuan-Ying Lai

Po-Wen Su

Yao-Jhan Wang

Chun-Mao Chiou

Jie-Ning Yang

Wen-Tsung Chang

Bo-Yu Su

Chang-Mao Wang

Hsin-Yu Hsieh

Chung-Yi Chiu

Shui-Yen Lu

Chien-Hao Chen

Chiu-Hsien Yeh

Chun-Chi Yu

Zhen Wu

Wen-Yen Huang

Chun-Wei Lin

Mei-Chin Chen

Ming-Hung Ling

A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

Method for correcting critical dimension measurements of lithographic tool

A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Metal gate structure and method of fabricating the same

A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

Method of forming a semiconductor device

A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

Etching back method

A semiconductor device includes a metal gate on a substrate, in which the metal gate includes a first work function metal (WFM) layer and the first WFM layer further includes a first vertical portion, a second vertical portion, wherein the first vertical portion and the second vertical portion comprise different heights, and a first horizontal portion connecting the first vertical portion and the second vertical portion.

Semiconductor device having asymmetric work function metal layer

A substance delivery device comprises a substrate, a plurality of dissolvable supporting structures and a plurality of carriers. The substrate attaches to a tissue. The dissolvable supporting structures are disposed on the substrate. The carriers are disposed on the dissolvable supporting structures and encapsulating substances. The present invention further provides a substance delivery method. The substance delivery device and the substance delivery method of present invention is advantageous for providing sustained release effect and rising the applicability of transdermal or transmucosal delivery techniques.

Substance delivery device and substance delivery method using the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.

Method for fabricating semiconductor device

Growing community of inventors

Chiayi, Taiwan

Kuan-Ying Lai