Mediatek Corporation

Kuan-Ta Chen

Sung-Han Wen

Yu-Hung Lin

Yu-Cheng Chang

Chuan-Hung Hsiao

Shih-Hsiung Chien

Wei-lin Chen

Wei-Hsin Tseng

Fong-Wen Lee

Chih-Ping Lin

Jing-Yi Huang

Pang-Yen Chin

Satya Narayana Ganta

A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a '0' state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.

Tri-level digital-to-analog converter element with mismatch suppression and associated method

The present invention provides a linear amplifier including an amplifier stage, a DC-shifting stage, a compensation network and a power stage. The amplifier stage is configured to generate a first signal and a second signal. The DC-shifting stage is configured to adjust a DC voltage of the first signal and a DC voltage of the second signal to generate an adjusted first signal and an adjusted second signal. The compensation network is configured to generate a first driving signal and a second driving signal according to the first signal, the second signal, the adjusted first signal and the adjusted second signal. The power stage is configured to generate an output signal according to the first driving signal and the second driving signal.

Amplifier output stage with DC-shifting circuit for high-speed supply modulator

A high-speed successive-approximation register analog-to-digital converter (SAR ADC) is shown. A digital-to-analog converter (DAC), a comparator, and a SAR logic circuit are configured to form a loop for successive approximation of a digital representation of an analog input. The SAR logic circuit includes a plurality of latches. Each latch uses a one-gate-delay circuit to wire the comparator to one bit-control terminal of the DAC.

High-speed successive-approximation register analog-to-digital converter

An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.

Amplifier circuit using voltage-to-current conversion and associated envelope tracking supply modulator using the same

An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

Operational amplifier using single-stage amplifier with slew-rate enhancement and associated method

A class-D amplifier with low pop-click noise is shown. A loop filter, a control signal generator, a first power driver, and a first feedback circuit are provided within the class-D amplifier to establish a first loop for signal amplification. The class-D amplifier further has a settling circuit and a pre-charging circuit. The settling circuit is configured to be combined with the loop filer and the control signal generator to establish a second loop to settle the loop filter and the control signal generator before the first loop is enabled. The pre-charging circuit is configured to pre-charge a positive output terminal and a negative output terminal of the first power driver.

Low pop-click noise class-D amplifier

An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal.

A multi-stage amplifier with a high signal-to-noise ratio is introduced. Multiple amplification stages are cascaded between an input terminal and an output terminal of the amplifier. A controller switches the output stage among the multiple amplification stages from a normal mode to an attenuation mode in response to the amplifier input being lower than the threshold. In the attenuation mode, the output stage provides an attenuation resistor coupled in series with the load resistor of the amplifier. Noise is successfully attenuated by the attenuation-mode output stage.

High signal-to-noise ratio amplifier with multiple output modes

The present invention provides an amplifier including a DAC, an analog signal processing circuit, a digital signal processing circuit, a signal detector and a driving stage is disclosed. The DAC is configured to perform a digital-to-analog conversion operation on a digital input signal to generate an analog input signal. The analog signal processing circuit is configured to generate a first processed signal according to the analog input signal and a feedback signal. The digital signal processing circuit is configured to process the digital input signal to generate a second processed signal. The signal detector is configured to detect strength of the digital input signal to generate a mode selection signal. The driving stage is configured to refer to the mode selection signal to receive one of the first processed signal and the second processed signal to generate an output signal, wherein the feedback signal is generated by the output signal.

Amplifier with signal dependent mode operation

An oscillation device includes an oscillator and a logic circuit. The oscillator generates an output oscillation signal. The logic circuit controls the oscillator according to the output oscillation signal, such that the output oscillation signal includes two different oscillation periods. The oscillation device may be used as a temperature-to-frequency converter without any bandgap reference circuit.

Oscillation device

A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.

High linearity digital-to-analog converter with ISI-suppressing method

An impedance circuit includes a first poly-resistor and a second poly-resistor. The first poly-resistor has a first terminal coupled to a first node, and a second terminal coupled to a second node. The second poly-resistor has a first terminal coupled to the first node, and a second terminal coupled to the second node. The resistance between the first terminal and the second terminal of the first poly-resistor is determined according to a first control voltage. The resistance between the first terminal and the second terminal of the second poly-resistor is determined according to a second control voltage. The first control voltage and the second control voltage are determined according to a first voltage at the first node and a second voltage at the second node.

Impedance circuit with poly-resistor

An impedance circuit includes a poly-resistor and a controller. The poly-resistor has a first terminal and a second terminal. The controller generates a first control voltage and a second control voltage. The resistance between the first terminal and the second terminal of the poly-resistor is determined according to the first control voltage and the second control voltage. The second control voltage is different from the first control voltage. The proposed impedance circuit can improve the linearity of the poly-resistor.

An amplifier circuit has a multi-stage amplifier, a compensation capacitor, and compensation circuits. The multi-stage amplifier has amplifiers cascaded between an input port and an output port of the multi-stage amplifier. The amplifiers include at least a first-stage amplifier, a second-stage amplifier and a third-stage amplifier. The compensation capacitor is coupled between the output port of the multi-stage amplifier and an output port of the first-stage amplifier. The compensation circuits include a first compensation circuit and a second compensation circuit. The first compensation circuit is coupled to the output port of the first-stage amplifier. The second compensation circuit is coupled to an output port of the second-stage amplifier.

Multi-stage amplifier circuit with zero and pole inserted by compensation circuits

A device for removing crosstalk includes a jack to form an electrical connection with a plug, and an audio unit to provide a left audio channel and a right audio channel to the plug. The audio unit includes a crosstalk cancellation circuit. The crosstalk cancellation circuit estimates the crosstalk between the left audio channel and the right audio channel to obtain an estimated right-to-left crosstalk and an estimated left-to-right crosstalk, and to remove the crosstalk by subtracting the estimated right-to-left crosstalk and the estimated left-to-right crosstalk from digital signals in the left audio channel and the right audio channel, respectively.

Growing community of inventors

Hsinchu, Taiwan

Kuan-Ta Chen