International Business Machines Corporation

National Yang Ming Chiao Tung University

Advanced Semiconductor Engineering, Inc.

Industrial Technology Research Institute

Massachusetts Institute of Technology

The Singer Company N.v.

Txc Corporation

Kuan-Neng Chen

Lia Krusin-Elbaum

Sampath Purushothaman

Dennis Merton Newns

Anna Wanda Topol

Phaedon Avouris

Bruce Kenneth Furman

Cornelia K Tsang

Yu-Ming Lin

Chung H Lam

Damon B Farmer

Solomon Assefa

Steven John Koester

Cheng-Ta Ko

Albert M Young

David Lee Rath

Wei-Chung Lo

Fei Liu

Edmund Juris Sprogis

Xiao Hu Liu

Yurii A Vlasov

John Christopher Arnold

Matthew R Wordeman

Glenn John Martyna

Bruce Gordon Elmegreen

Niranjana Ruiz

Yuri A Vlasov

Min-Fong Shu

Yi-Hsiu Tseng

Shu-Chiao Kuo

Matthew Joseph Breitwisch

Yao-Jen Chang

Hung-Ming Chen

Kuo-Hua Chen

Wen-Wei Shen

Chuan Seng Tan

Rafael Reif

Chih-Hung Chiu

Andy Fan

Han-Wen Hu

Ming-Fang Lai

Yi-Chieh Tsai

Tzu-Hua Lin

Shih-Wei Li

Sheng-Yao Hsu

Demin Liu

Yan-Pin Huang

Chi-Chung Chang

Yen-Chi Chen

Jian-Yu Shih

A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.

Bonding element and method for manufacturing the same

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

Bonding structure for semiconductor package and method of manufacturing the same

A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.

Bonding structure and method of fabricating the same

A bonding structure includes a substrate having a top surface and including at least one bonding pad. Each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface. A semiconductor element includes at least one pillar. Each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.

Sloped bonding structure for semiconductor package

A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided.

Semiconductor device, manufacturing method and stacking structure thereof

The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.

Semiconductor bonding structure

A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

Submicron connection layer and method for using the same to connect wafers

Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate.

Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed

Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Graphene channel-based devices and methods for fabrication thereof

The present invention provides a TSV-based oscillator WLP structure and a method for fabricating the same. The method of the present invention comprises steps: providing a silicon base having an oscillator unit disposed thereon; forming on the silicon base at least one package ring surrounding the oscillator unit; and disposing a silicon cap on the package ring to envelop the oscillator unit. The present invention adopts a cap and a base, which are made of the same material, to effectively overcome the problem of thermal stress occurring in a conventional sandwich package structure. Further, the present invention elaborately designs the wiring on the lower surface of the base to reduce the package size and decrease consumption of noble metals.

Through silicon via-based oscillator wafer-level-package structure and method for fabricating the same

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Heterostructure containing IC and LED and method for fabricating the same

An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.

Integrated circuit device

Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

Growing community of inventors

Hsinchu, Taiwan

Kuan-Neng Chen