Taiwan Semiconductor Manufacturing Comp. Ltd.

Young Optics Inc.

Kuan-Lun Cheng

Chih-Hao Wang

Ching-Wei Tsai

Kuo-Cheng Chiang

Shi Ning Ju

Kuo-Cheng Ching

Cheng-Chi Chuang

Li-Zhen Yu

Lin-Yu Huang

Yu-Xuan Huang

Kuan-Ting Pan

Chia-Hao Chang

Mao-Lin Huang

Jia-Ni Yu

Chung-Wei Hsu

Lung-Kun Chu

Cheng-Ting Chung

Sai-Hooi Yeong

Shi-Ning Ju

Hou-Yu Chen

Jung-Chien Cheng

Zhiqiang Wu

Guan-Lin Chen

Wen-Hsing Hsieh

Yi-Bo Liao

Wang-Chun Huang

Pei-Yu Wang

Chung-Wei Wu

Min Cao

Kai-Chieh Yang

Chi-Hsing Hsu

Bo-Feng Young

Huan-Chieh Su

Zhi-Chang Lin

Chih-Ching Wang

Chun-Yuan Chen

Wei Ju Lee

Jon-Hsu Ho

Yi-Ruei Jhan

Chien Ning Yao

Yen-Ming Chen

Lo-Heng Chang

Chun-Fu Cheng

Wen-Ting Lan

Jiun-Jia Huang

Tetsu Ohtou

Kuo-cheng Chiang

Wen-Yuan Chen

Li-Yang Chuang

Wei-Yang Lee

Yi-Hsun Chiu

Kai-Hsuan Lee

Tzer-Min Shen

Teng-Chun Tsai

Jia-Chuan You

Chung-Cheng Wu

Wei-Hao Wu

Chi-On Chui

Ting-Hung Hsu

Chun-Fu Lu

Keng-Chu Lin

Jam-Wem Lee

Yasutoshi Okuno

Kuo-Ji Chen

Shang-Wen Chang

Jiann-Tyng Tzeng

Wei-Cheng Lin

Yih Wang

Chung-Hui Chen

Chih-Yu Chang

Jung-Hung Chang

Yi-Ming Sheu

Pei-Hsun Wang

Tsung-Hsing Yu

Wei-An Lai

Ming-Chang Wen

Jui-Chien Huang

Bo-Yu Lai

Chia-en Huang

Chih-Pin Tsao

Li-Shyue Lai

Chien-Ning Yao

Wei-Szu Lin

Yu-Chen Chang

Chung-Liang Cheng

Chia-En Huang

Katherine H Chiang

Ka-Hing Fung

Yi-Hsiung Lin

Sheng-Tsung Wang

Jin Cai

Yu-Ting Cheng

Ke-Wei Su

Shui-Ming Cheng

Huan-Tsung Huang

Yin-Pin Wang

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

Gate-all-around structure with self substrate isolation and methods of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over nanostructures. The gate structure includes a gate dielectric layer, and a fill layer over the gate dielectric layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a gate spacer layer formed adjacent to the gate structure. The semiconductor device structure includes an insulating layer formed over the protection layer, and the insulating layer is in direct contact with the gate spacer layer.

Semiconductor transistor device structure including nanostructure and gate structure with protection layer and fill layer and method for forming the same

A semiconductor device structure includes a fin structure over a semiconductor substrate and a dummy gate stack formed over the fin structure and having a first sidewall and an opposite second sidewall. The semiconductor device structure also includes a first and second source or drain (S/D) structures in the fin structure and respectively adjacent to the first and second sidewalls of the dummy gate stack. The semiconductor device structure further includes an isolation feature formed in the fin structure below the dummy gate stack and having a third sidewall and an opposite fourth sidewall. A first end of the third sidewall overlaps the first end of the fourth sidewall. A second end of the third sidewall is in direct contact with a bottom of the dummy gate stack. A second end of the fourth sidewall is separated from the bottom of the dummy gate stack.

Structure of isolation feature of semiconductor device structure

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes semiconductor material layers stacked above a substrate along a first direction and a gate structure wrapping around the semiconductor material layers. The semiconductor structure further includes an epitaxial structure coupled to the semiconductor material layers in a second direction that is different from the first direction and a SiGe-containing layer located below the epitaxial structure. In addition, a material of the SiGe-containing layer is different from a material of the epitaxial structure, the SiGe-containing layer comprises a first portion with a first thickness in the first direction, and a second portion with a second thickness in the first direction, and the second thickness is smaller than the first thickness.

Gate-all around transistor with isolating feature under source/drain

FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Fin-like field effect transistor patterning methods for achieving Fin width uniformity

A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

Semiconductor device with air gaps and method of fabrication thereof

A semiconductor device includes a substrate, an interconnect, a second transistor, and a sensing film. The substrate includes devices disposed therein. The interconnect is disposed on the substrate and electrically coupled to the devices, where the interconnect includes a plurality of build-up layers and a through hole formed therein. The first transistor is disposed in the interconnect and vertically extends through at least one of the plurality of build-up layers, and the first transistor is electrically coupled to a first device of the devices through the interconnect. The second transistor is disposed in the interconnect and vertically extends through the at least one of the plurality of build-up layers, and the second transistor is electrically coupled to a second device of the devices through the interconnect, where the first transistor and the second transistor are laterally separated from one another through the through hole. The sensing film is disposed on the interconnect and further extends into the through hole, where the sensing layer is laterally disposed between the first transistor and the second transistor.

Semiconductor device and manufacturing method thereof

A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

Stacking CMOS structure

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

2D-channel transistor structure with asymmetric substrate contacts

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

FinFET structure with airgap and method of forming the same

A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.

Semiconductor devices with backside power rail and backside self-aligned via

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Gap-insulated semiconductor device

The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

High-voltage nano-sheet transistor

Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Semiconductor device having backside via and method of fabricating thereof

A biosensor including a first sensor, a second sensor, a patterned dielectric layer and a cover is provided. The first sensor includes a first voltage-reference device and a first bio-sensing device. The second sensor is disposed adjacent to the first sensor, the second sensor includes a second voltage-reference device and a second bio-sensing device, the first sensor is spaced apart from the second sensor by a lateral distance, and the lateral distance is greater than a half of an average lateral dimension of the first voltage-reference device and the second voltage-reference device. The patterned dielectric layer includes sensing wells located above the first voltage-reference device, the first bio-sensing device, the second voltage-reference device and the second bio-sensing device. The cover includes fluid channels communicating with the sensing wells.

Biosensor

Growing community of inventors

Hsin-Chu, Taiwan

Kuan-Lun Cheng