Taiwan Semiconductor Manufacturing Comp. Ltd.

Young Optics Inc.

Kuan-Lun Cheng

Chih-Hao Wang

Ching-Wei Tsai

Kuo-Cheng Chiang

Shi Ning Ju

Kuo-Cheng Ching

Cheng-Chi Chuang

Li-Zhen Yu

Lin-Yu Huang

Yu-Xuan Huang

Kuan-Ting Pan

Sai-Hooi Yeong

Chia-Hao Chang

Mao-Lin Huang

Jia-Ni Yu

Chung-Wei Hsu

Lung-Kun Chu

Cheng-Ting Chung

Shi-Ning Ju

Hou-Yu Chen

Jung-Chien Cheng

Zhiqiang Wu

Guan-Lin Chen

Wen-Hsing Hsieh

Yi-Bo Liao

Wang-Chun Huang

Pei-Yu Wang

Chung-Wei Wu

Min Cao

Kai-Chieh Yang

Chi-Hsing Hsu

Chi-Yi Chuang

Bo-Feng Young

Huan-Chieh Su

Zhi-Chang Lin

Chih-Ching Wang

Chun-Yuan Chen

Wei Ju Lee

Jon-Hsu Ho

Yi-Ruei Jhan

Chien Ning Yao

Yen-Ming Chen

Lo-Heng Chang

Chun-Fu Cheng

Wen-Ting Lan

Jiun-Jia Huang

Tetsu Ohtou

Wen-Yuan Chen

Li-Yang Chuang

Wei-Yang Lee

Yi-Hsun Chiu

Kai-Hsuan Lee

Tzer-Min Shen

Kuo-cheng Chiang

Teng-Chun Tsai

Jia-Chuan You

Chung-Cheng Wu

Wei-Hao Wu

Chi-On Chui

Ting-Hung Hsu

Keng-Chu Lin

Jam-Wem Lee

Yasutoshi Okuno

Kuo-Ji Chen

Shang-Wen Chang

Chun-Fu Lu

Jiann-Tyng Tzeng

Wei-Cheng Lin

Yih Wang

Chung-Hui Chen

Chih-Yu Chang

Jung-Hung Chang

Yi-Ming Sheu

Pei-Hsun Wang

Tsung-Hsing Yu

Ming-Chang Wen

Wei-An Lai

Jui-Chien Huang

Bo-Yu Lai

Chia-en Huang

Chih-Pin Tsao

Li-Shyue Lai

Chien-Ning Yao

Wei-Szu Lin

Yu-Chen Chang

Chia-En Huang

Katherine H Chiang

Ka-Hing Fung

Yi-Hsiung Lin

Sheng-Tsung Wang

Jin Cai

Yu-Ting Cheng

Ke-Wei Su

Shui-Ming Cheng

Huan-Tsung Huang

Yin-Pin Wang

A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

Stacking CMOS structure

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

2D-channel transistor structure with asymmetric substrate contacts

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

FinFET structure with airgap and method of forming the same

A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.

Semiconductor devices with backside power rail and backside self-aligned via

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Gap-insulated semiconductor device

The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

High-voltage nano-sheet transistor

Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Semiconductor device having backside via and method of fabricating thereof

A biosensor including a first sensor, a second sensor, a patterned dielectric layer and a cover is provided. The first sensor includes a first voltage-reference device and a first bio-sensing device. The second sensor is disposed adjacent to the first sensor, the second sensor includes a second voltage-reference device and a second bio-sensing device, the first sensor is spaced apart from the second sensor by a lateral distance, and the lateral distance is greater than a half of an average lateral dimension of the first voltage-reference device and the second voltage-reference device. The patterned dielectric layer includes sensing wells located above the first voltage-reference device, the first bio-sensing device, the second voltage-reference device and the second bio-sensing device. The cover includes fluid channels communicating with the sensing wells.

Biosensor

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Semiconductor device structure

Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

Semiconductor device and method of forming thereof

A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Nanosheet devices with hybrid structures and methods of fabricating the same

A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Self-aligned spacers for multi-gate devices and method of fabrication thereof

Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

Gate all around transistor device and fabrication methods thereof

A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

Method for metal gate cut and structure thereof

A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

Fin isolation structures of semiconductor devices

Growing community of inventors

Hsin-Chu, Taiwan

Kuan-Lun Cheng