United Microelectronics Corp.

Kuan-Liang Liu

Shih-Yin Hsiao

Ching-Chung Yang

Ping-Hung Chiang

Chih-Chung Wang

Wen-Fang Lee

Nien-Chung Li

Kai-Kuen Chang

A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

Transistor structure

A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

High voltage semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

Method for preventing dishing during the manufacture of semiconductor devices

A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.

Method of fabricating a transistor with reduced hot carrier injection effects

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric layer is disposed below said gate electrode and protrudes therefrom to said drain, thereby separating said gate electrode and said drain by a substantial distance to reduce gate induced drain leakage.

Semiconductor device and method for forming the same

A method for fabricating isolation device is disclosed. The method includes the steps of: providing a substrate; forming a shallow trench isolation (STI) in the substrate, the STI includes a first STI and a second STI, and the first STI surrounds a first device region and the second STI surrounds a second device region; forming a first doped region between and contact the first STI and the second STI; and forming a first gate structure on the first doped region, the first STI and the second STI.

Growing community of inventors

Hsinchu County, Taiwan

Kuan-Liang Liu