Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Nyquest Corporation Limited

Kuan-Jung Chen

Tsung-Lin Lee

Wen-Chih Chiang

Cheng-Hung Wang

Shiuan-Jeng Lin

Chun-Ming Lin

Chih-Mu Huang

I-Chih Chen

Ting-Chun Kuan

Hung-Lin Chen

Kai-Di Wu

Chung-Ming Lin

Ming-Feng Lee

Ming-Dou Ker

Wei-Ming Chen

Chung-Yu Wu

Yu-Ting Cheng

Fu-Tsun Tsai

Yu-Chu Chen

Sheng-Lin Hsieh

Chih-Hsuan Lee

Tzu-Hao Yeh

Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.

Bipolar junction transistor (BJT) and fabricating method thereof

Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

Structures and methods for trench isolation

Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Structures and methods for reducing process charging damages

The reflectance of a low-reflectance alignment mark is increased by coating the alignment mark with a high-reflectance film layer. This improves the strength of the light signal and reduces variation in the light signal.

Alignment mark structure and method for making

A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.

Semiconductor device and manufacturing method thereof

Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

Method for forming a crystalline protective polysilicon layer

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain feature in the substrate, protruding from the substrate, and on a sidewall surface of the gate structure. The semiconductor device structure also includes an insulating barrier structure in the substrate and partially covering the bottom and sidewalls of the source/drain feature.

Source/drain structure with barrier in FinFET device and method for forming the same

A wireless charging device includes a wireless charging transmitter transmitting a charging signal to a signal gain module to generate at least one gain signal. The signal gain module includes an insulation substrate with an upper surface thereof provided with a first conductive wire. The first conductive wire makes at least one turns arranged along the inner edge of the insulation substrate. The lower surface of the insulation substrate is provided with a second conductive wire whose position corresponds to the position of the first conductive wire. A connecting element is arranged between the first conductive wire and the second conductive wire, such that the first conductive wire is electrically connected to the second conductive wire through the connecting element. The present invention provides a charging signal with high intensity to avoid the low charging efficiency caused by deflection and too long a distance.

Wireless charging device

A radio frequency transmission method and a device thereof are provided. The method includes: transmitting a radio frequency command by a radio frequency reader; receiving the radio frequency command by a radio frequency tag, wherein the radio frequency command includes bits; determining a logic level of each of the bits based upon a time length of each of the bits at a voltage level of a voltage waveform by the radio frequency tag; and determining whether to transmit a response signal in response to the radio frequency reader based upon the logic level of each of the bits by the radio frequency tag.

Growing community of inventors

Tainan, Taiwan

Kuan-Jung Chen