Via Technologies, Inc.

Via Alliance Semiconductor Co., Ltd.

Kuan-Jui Ho

Hsiu-Ming Chu

Zheng Wang

Lin Li

Mengchen Yang

Xiaoyang Li

Zongpu Qi

Yi-Hsiang Wang

Fangfang Wu

Jin Yu

Lei Meng

Chung-Che Wu

Shican Luo

Hsiu Ming Chu

Chung-Ching Huang

Jui-Ming Wei

Ming-Wei Hsu

Jen-Chieh Chen

Wen-Pin Chiang

Min-Hung Chen

Wen-Yun Chen

Hsiou-Ming Chu

Tsung-Pin Yang

An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.

Electronic apparatus and method of extending peripheral device

The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: fetching a string to be compressed from a data buffer; storing instances corresponding to the string in an intermediary buffer; issuing a hash request to a hash matcher for each instance, issuing a data request to an LSM (longest string matcher) according to a first reply sent by the hash matcher, and updating a state, a match length and a match offset of the instance according to a second reply sent by the LSM; and outputting the result to a formatter according to the state, the match length and the match offset of each instance in the original order of the associated substrings that appeared in the string.

Methods for accelerating hash-based compression and apparatuses using the same

The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: receiving, by a plurality of hash functions, a plurality of substrings from an FSM (Finite-State Machine) in parallel; mapping, by each hash function, the received substring to a hash index and directing a selector to connect to one of a plurality of match paths according to the hash index; transmitting, by a matcher of each connected match path, a no-match message to the FSM when determining that a hash table does not contain the received substring; and transmitting, by the matcher of each connected match path, a match message and a match offset of the hash table to the FSM when determining that the hash table contains the received substring, wherein the match offset corresponds to the received substring.

A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function.

System and method for assigning virtual functions and management host thereof

A system and a method for managing an expansion read-only memory (ROM), and a management host thereof are provided. The management host is connected with a computer host through a bridge. The management host establishes an address lookup table to assign a virtual function and an expansion ROM corresponding to the virtual function. When a request is issued by the computer host to obtain a size of the expansion ROM, the management host provides data in a shadow register block corresponding to the expansion ROM to the computer host according to the address lookup table. The computer host assigns a memory block in the computer host to the expansion ROM according to the data in the shadow register block. When a request is issued by the computer host to obtain data of the expansion ROM through the bridge, the management host provides the data of the expansion ROM to the computer host according to the memory block.

System and method for managing expansion read-only memory and management host thereof

A storage media control method, by which a data strobe signal is shifted by different phase shifts at different time intervals during a write-leveling operation to be received by a storage media and compared to a clock signal for returning a data signal. At the storage media side, during the write-leveling operation, a synchronous transmission between the received data strobe signal and the clock signal causes a transition event at the data signal. The number of transition-event occurrences is counted. When the count shows that just one transition event has occurred over a full round of phase shift tests of the data strobe signal, the phase shift corresponding to the transition event is used in the adjustment of the data strobe signal, which is received by the storage media as the data extraction reference of a write operation.

Data storage device, storage media controller and storage media control method

A computer apparatus and a method for distributing interrupt tasks thereof are provided. The computer apparatus has a plurality of CPUs and a chipset, and the chipset is electrically coupled to each of the CPUs. The chipset is configured for receiving an interrupt request sent from an external hardware device and judging whether or not a task type corresponding to the interrupt request has ever been performed by any one of the CPUs. If a judging result thereof is yes, the chipset assigns the interrupt request to the CPU that has ever performed the task type, so as to perform a corresponding interrupt task.

Computer apparatus and method for distributing interrupt tasks thereof

A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control request signal, the chipset turns off the input buffer.

Multi-processor system supporting dynamic power saving and dynamic power saving method thereof

In a computer system including a central processing unit, a system memory, a south bridge module, a north bridge module and multiple hard disk drives, a RAID control function is exhibited. The method includes steps of: issuing a command addressing to the south bridge module by the central processing unit; and performing a fault-tolerant computing operation in the north bridge module while exempting from transmitting the command to the south bridge module when the command contains a specified address data.

RAID control method and core logic device having RAID control function

RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data. The timing for performing the fault-tolerant data computing operation is determined by accessing a data stored in one of the hard disk drives, detecting a partial data length of a data stream having been transmitted from the hard disk drive to the computer system, issuing a triggering signal when the data length has reached a unitary length less than the total length of the data stream, and then performing the fault-tolerant data computing operation with the unitary length of data in response to the triggering signal.

Computer system having raid control function and raid control method

A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Methods and systems for adjusting clock frequency

A method of power management of a CPU connects to a plurality of host bridges. The method is applied to a CPU connecting to the host bridges. When the host bridges are detected as no bus master signal being received, a command is transmitted to force the host bridges not to transmit the bus master signal to the CPU when they receive the bus master signal. After the CPU enters the C3 state, if the host bridges are detected that any one of the host bridges receives the bus master signal, the CPU is forced to quit the C3 state, and the host bridges are forced to transmit the bus master signal to the CPU.

Method of power management of a central processing unit connecting with a plurality of host bridges

A power management device for multiprocessor systems and method thereof applied to force individual processor entering or leaving of a C3 state are disclosed. The device includes at least one checking unit, a plurality of recording units and a plurality of arbiters. The checking unit receives an event from a peripheral device, checks which processor the event corresponds and sends a checking signal. The event is received and recorded by one of the recording units according to the checking signal. Once the recording unit has no record of the received event, the corresponding processor turns the corresponding arbiter off and sends an entering C3 state command. A first control signal is sent to the processor according to the entering C3 state command so as to force the processor into the C3 state.

Power management device for multiprocessor system and method thereof

A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot reset packet cannot be executed by the high-speed PCI device, the host controller chipset can respectively transmit a trigger signal and a PCI reset signal to each corresponding reset signal generator through a trigger signal line and a PCI reset signal line, and further the reset signal generator operates to generate a basic resetting signal. Finally, the basic resetting signal will be transmitted to the corresponding high-speed PCI device through a basic reset signal line such that the system can be used to operate the basic resetting action without restarting power.

High-speed PCI interface system and a reset method thereof

The present invention relates to a method for configuring a Peripheral Component Interconnect Express (PCIE). A plurality of PCIE parameters are stored in a storage unit. When a computer system starts up, a North Bridge chip is driven to read the PCIE parameters in the storage unit for configuring the PCIE. According to the configuration method of the present invention, when the computer system starts up, the North Bridge chip and the storage unit are enabled first. Then, the North Bridge chip is driven to read the PCIE parameters. Finally, the North Bridge chip proceeds with initialization according to the PCIE parameters to configure PCIE.

Growing community of inventors

Taipei, Taiwan

Kuan-Jui Ho