Mediatek Corporation

Kuan-Hua Chao

Tse-Hsiang Hsu

Jeng-Horng Tsai

Chih-Ching Chen

Ping-Ying Wang

Yan-Bin Luo

Kuo-Jung Lan

Chuan Liu

Ming-Jiou Yu

Shiue-Shin Liu

Shu-Hung Chou

Chia-Wei Liao

Jong-Woei Chen

Yu-Bang Nian

Tzu-Li Hung

Chun-Yu Lin

Pao-Cheng Chiu

Bing-Yu Hsieh

Meng-Ta Yang

Yi-Hsien Cho

Juei-Ting Sun

Chih-Chien Hung

Chien-Hua Wu

Po-Hsun Huang

Yu-Ming Wen

Hong-Sing Kao

Chang-Yi Hsu

A wireless communication method of a wireless device is provided, wherein the wireless communication method comprises the steps of: building links with a plurality of electronic devices, respectively; and simultaneously using a time division multiplex mode and a frequency division multiplex mode to communicate with the plurality of electronic devices.

Wireless communication method and associated wireless communication device

A detecting circuit includes: a testing signal generator, arranged to selectively generate a testing signal having a first signal edge or a second signal edge to a connecting port; and a detector, arranged to detect a first detect signal on the connecting port after the testing signal having the first signal edge is coupled to the connecting port, and to detect a second detect signal on the connecting port after the testing signal having the second signal edge is coupled to the connecting port; wherein the detector is further arranged to determine if an external circuit element is coupled between the connecting port and a reference voltage according to the first detect signal and the second detect signal.

Detecting circuit and related circuit detecting method

An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.

Interpolator and interpolation cells with non-uniform driving capabilities therein

A method for performing adaptive equalization includes: dynamically detecting current levels of a plurality of sets of pattern levels respectively corresponding to a plurality of data patterns, wherein each set of the sets of pattern levels includes a previous level, a current level, and a next level respectively corresponding to one of the plurality of data patterns; and dynamically calculating a plurality of data decision levels according to the current levels of the sets of pattern levels, for use of data decision, wherein each data decision level of at least one portion of the plurality of data decision levels is not equal to zero, and the data decision levels are dynamically adjusted in accordance with the current levels of the sets of pattern levels, in order to enhance a signal-to-noise ratio (SNR). An associated method for performing adaptive equalization is also provided. Associated apparatus are also provided.

Methods for performing adaptive equalization and associated apparatus

A detecting circuit includes: a first offset generating circuit, arranged to apply a first offset to an input signal pair and accordingly generate a first output signal pair; and a first sampling circuit, coupled to the first offset generating circuit, the first sampling circuit arranged to sample the first output signal pair to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair, and the first sampling circuit is controlled by a first signal that is irrelevant to the input signal pair.

Detecting circuit and related detecting method

A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Circuit and method for controlling mixed mode controlled oscillator and CDR circuit using the same

A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.

Clock generation devices and methods

A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair.

A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL generates the output clock signal according to a second clock signal.

Communication systems and clock generation circuits thereof with reference source switching

A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.

Communication systems, clock generation circuits thereof, and method for generating clock signal

A calibration circuit for calibrating a differential driver with a differential output port including a first output node and a second output node includes: a comparing circuit arranged to receive a first output voltage corresponding to the first output node and a second output voltage corresponding to the second output node, and generate a comparison result according to the first output voltage, the second output voltage, and a predetermined voltage; and a controlling circuit coupled to the comparing circuit, a first resistive element and a second resistive element. The controlling circuit is arranged to adjust the first resistive element and the second resistive element according to the comparison result, wherein the first resistive element is coupled between the first output node and a reference voltage, and the second resistive element is coupled between the second output node and the reference voltage.

Differential driver with calibration circuit and related calibration method

A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.

Frequency divider, frequency dividing method thereof, and phase locked loop utilizing the frequency divider

The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.

Serial link transmitter

A driving circuit includes: a first reference current source injects a reference current; each first switch unit is coupled between the first reference current source and one of first and second output ports; a second reference current source sinks the reference current; each second switch unit is coupled between the second reference current source and one of the output ports; a load unit is coupled between the output ports, and a common voltage is applied onto the load unit; and a calibration module calibrates an impedance of the load unit according to a voltage at one of the output ports, and the voltage is generated due to the reference current passing through one of the first switch units, the load unit, and one of the second switch units.

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Taipei, Taiwan

Kuan-Hua Chao