United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Kuan-Chun Lin

Chi-Mao Hsu

Feng-Yi Chang

Fu-Che Lee

Shih-Fang Tzou

Yen-Chen Chen

Kuo-Chih Lai

Nien-Ting Ho

Tsuo-Wen Lu

Shu-Yen Chan

Shih-Min Chou

Tien-Chen Chan

Ger-Pin Lin

Yang-Ju Lu

Wei-Ming Hsiao

Ching-Yun Chang

Yun-Tzu Chang

Shih-Kuei Yen

Wei-Chuan Tsai

Kuo-Chin Hung

Shih-Cheng Chen

Yung-Teng Tsai

Chung-Chih Hung

Chi-Hung Chan

Chih-Chieh Chou

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Method for fabricating semiconductor device

A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

Buried word line structure and method of making the same

Semiconductor device and method for fabricating the same

A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.

Semiconductor structure and fabrication method thereof

A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.

Test structure for electron beam inspection and method for defect determination using electron beam inspection

Growing community of inventors

Tainan, Taiwan

Kuan-Chun Lin