Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Kuan-Chao Chen

Shih-Yen Lin

Si-Chen Lee

Samuel C Pan

Chi-Wen Liu

Chong-Rong Wu

Hsuan-An Chen

Yu-Wei Zhang

Chi Chen

Lun-Ming Lee

A method includes forming an interlayer dielectric (ILD) layer over a transistor; forming a first inter-metal dielectric (IMD) layer over the ILD layer; etching a via opening extending through the first IMD layer; forming a first 2-D material layer lining along sides and a bottom of the via opening; depositing a first metal in the via opening and over the first 2-D material layer; performing a chemical mechanism polishing (CMP) process to the first metal until the first IMD layer is exposed; forming a second IMD layer over the first IMD layer; etching a trench in the second IMD layer; forming a second 2-D material layer lining along sides and a bottom of the trench; and depositing a second metal over the second 2-D material layer at a temperature lower than a temperature of depositing the first metal over the first 2-D material layer.

Integrated circuit structure and method for forming the same

A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.

2D crystal hetero-structures and manufacturing methods thereof

A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.

Source/drain contact with 2-D material

A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.

Method of forming a semiconductor device using layered etching and repairing of damaged portions

In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoSlayer. Source and drain electrodes are formed on the MoSlayer. The MoSlayer is treated with low-power oxygen plasma. A gate dielectric layer is formed on the MoSlayer. A gate electrode is formed on the gate dielectric layer. An input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

Growing community of inventors

Tainan, Taiwan

Kuan-Chao Chen