Hefei Core Storage Electronic Limited

Kuai Cao

Chih-Ling Wang

Dong Dong Yao

Qi-Ao Zhu

En Yang Wang

Jing Zhang

Xin Wang

Dong Sheng Rao

Yun Zhang

Xu Hui Cheng

Yue Hu

Yang Chen

Qin Qin Tao

Wen Qing Lv

Ya Jie Guo

Wan-Jun Hong

Yin Ping Gao

A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: creating a physical block management table for managing physical blocks; selecting at least one physical block to be refreshed based on the physical block management table when power is restored after an abnormal power loss; in response to a number of the at least one physical block to be refreshed being greater than 1, determining at least one current state and at least one category of the at least one physical block to be refreshed; and executing at least one second write operation based on the current state and the category together when executing a first write operation. The first write operation includes writing user data into a cache. The second write operation includes writing data stored in a physical block to be refreshed into a first physical block.

Memory management method for evenly distributing input output latency time, memory storage device, and memory control circuit unit

A data writing method, a memory storage device, and a memory control circuit unit are provided. The data writing method includes the following: calculating a first number according to a ratio of a capacity of at least one first system table to a capacity of a physical block; calculating a second number according to a ratio of a capacity of at least one second system table to the capacity of the physical block; and obtaining at least one physical block from a plurality of physical blocks as a first virtual block and a second virtual block based on the first number and the second number respectively.

Data writing method, memory storage device and memory control circuit unit

A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: in response to receiving a data management command from a host system, calculating a plurality of occupied capacities required for a plurality of system management information respectively stored in a plurality of physical erasing units based on a capacity of an allocation unit; executing a data consolidation operation based on the occupied capacities, and in response to an occupied capacity being greater than a capacity of a physical erasing unit, copying system management information corresponding to the occupied capacity to at least one first physical erasing unit; and in response to a sum of at least one occupied capacity not being greater than the capacity of the physical erasing unit, copying at least one system management information corresponding to the at least one occupied capacity to a second physical erasing unit.

Memory management method for improving the utilization rate, memory storage device, and memory control circuit unit

A data arrangement method based on file system, a memory storage device and a memory control circuit unit are disclosed. The method includes: analyzing a file system stored in a system region to obtain a plurality of first logical units to which a first file belongs and first distribution information of a plurality of first physical units in a storage region, wherein the first physical units are mapped by the first logical units; determining whether to activate a data arrangement operation on the first file according to the first distribution information; after the data arrangement operation on the first file is activated, reading first data belonging to the first file from the first physical units; and writing, sequentially, the read first data to at least one second physical unit in the storage region.

Data arrangement method based on file system, memory storage device and memory control circuit unit

A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: setting preset read count thresholds corresponding to physical erasing units respectively; in a background operation, in response to a read count of a first physical erasing unit in the physical erasing units being greater than its corresponding preset read count threshold, reading word lines in the first physical erasing unit to obtain first error bit amounts; determining whether a refresh operation needs to be performed on the first physical erasing unit according to first error bit amounts; in response to no need to perform the refresh operation on the first physical erasing unit, selecting a first word line with the largest first error bit amount in the word lines, and detecting a voltage distribution variation of the first word line; and calculating a new read count threshold of the first physical erasing unit according to the voltage distribution variation.

Memory control method, memory storage device and memory control circuit unit

A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

Performance match method of memory, memory storage device and memory control circuit unit

A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.

Memory polling method, memory storage device and memory control circuit unit

A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

Mapping table updating method, memory storage device and memory control circuit unit

A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.

Data storing allocation method, memory storage apparatus and memory control circuit unit

A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.

Timer calibration method and electronic device

A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

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Anhui, China

Kuai Cao