Skhynix Inc.

Ku Ik Kwon

Kyeong Seok Kim

Byoung Min Jin

Yong Joon Joo

Gyu Yeul Hong

Su Ik Park

Byong Woo Ryu

Min Gu Kang

Jin Won Jang

Na Young Lee

Hyun Jin Chung

Jun Han Lee

A storage device may generate mapping information between a plurality of memory regions and one or more namespaces. The storage device may record information on empty memory regions among the plurality of memory regions in an empty table, and may determine empty memory regions to be mapped to a target namespace among the empty memory regions recorded in the empty table.

Storage device translating logical address on the basis of sequentiality of namespace, and method thereof

Storage devices, methods of operating storage devices, and computing systems including storage devices are disclosed. In an embodiment, a storage device may include a plurality of memory devices and a memory controller for controlling the plurality of memory devices to process a request of a host in accessing plurality of memory devices, wherein the memory controller is configured to allocate the plurality of memory devices to a plurality of functions, allocate a plurality of request slots allowed to process the request per unit time for each of the plurality of functions, determine idle request slots other than active request slots being used to process the request among the plurality of request slots allocated to each of the plurality of functions, and control an internal operation of the plurality of memory devices based on at least one target function including the idle request slots among the plurality of functions.

Storage device, method of operating the same, and computing system including the storage device

Disclosed are a controller and an operating method thereof. According to an embodiment of the present disclosure, a controller that controls a memory device, comprises: a host interface for determining a remaining resource index and outputting a task scheduling instruction when a data throughput determined based on data inputted/outputted between a host and the controller is lower than a maximum throughput required under a current workload pattern; and a processor for: selecting, in response to the task scheduling instruction, at least one of a plurality of internal tasks based on the remaining resource index and resource consumption indexes of the respective internal tasks, and performing the selected internal task while performing an input/output task.

Controller and method of performing internal operation thereof

A controller includes at least one register configured to store a doorbell regarding a submission queue storing at least one request generated by a host, a first cache configured to store data corresponding to a first result of an operation performed in response to the at least one request, a second cache configured to store data corresponding to a second result of an operation performed in response to a read look ahead (RLA) request generated based on the at least one request, and a cache size manager configured to adjust a size of the second cache based on an update cycle of the doorbell and a change of a number of the at least one request corresponding to the doorbell.

Apparatus and method for adjusting cache allocated for read look ahead

A storage device, a controller, and a method for performing global wear-leveling may count write counts of a plurality of respective cores in each of a plurality of logical areas each including logical block address groups of the plurality of cores, determine, on the basis of degradation counts of the plurality of cores, a first core and a second core for which data swap is to be performed, determine a target logical area among the plurality of logical areas on the basis of a write count of the first core and a write count of the second core, and perform data swap between a first logical block address group of the first core included in the target logical area and a second logical block address group of the second core included in the target logical area.

Storage device, controller and method for performing global wear-leveling

The storage device may receive a condition for a down-time mode from the host. The storage device may cache, when the condition for the down-time mode is determined as satisfied, at least a part of update data units in the update cache. The storage device may process a read command received from the host in the down-time mode based on update data units cached in the update cache.

Storage device caching update target data unit while entering down-time mode and operating method of the storage device

Provided herein is a memory controller for controlling a memory device. The memory controller includes a workload detector configured to determine a change in workload based on reception of a changed request from a host or a change in clock received from an external device, a device performance controller configured to determine, if the workload is determined as changed, read performance based on a ratio of a size of data output to the host to a size of data requested from the host every preset period and configured to output a read-look-ahead (RLA) command to the memory device based on the determined read performance, a buffer memory configured to store data read from the memory device in response to the RLA command and a memory size controller configured to control a size of the buffer memory. The RLA command instructs to output data which is frequently requested from the host.

Memory controller and method of operating the same

Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may include a plurality of cores, a control core, and a shared memory. When processing the event, the control core may select a first core executing a target job requiring distributed execution among the plurality of cores, and the first core may run a first firmware among the plurality of firmwares to execute the target job. The control core may select a second core to execute the target job together with the first core, and may control the second core to run the first firmware. The control core may control the first core and the second core to perform distributed execution of the target job.

Memory system and operating method thereof

Electronic devices are disclosed. In some implementations, an electronic device includes a device interface to provide an interface to a host and detect link information associated with a bandwidth provided by the device interface in communicating with the host, a processor coupled to the device interface to be in communication with the host, and structured to be operable to control operations of the electronic device in response to a request received from the host through the device interface, and a clock generator coupled to provide the device interface and the processor with clock signals to be used to operate the device interface and the processor. The processor is configured to adjust frequencies of the clock signals based on the link information.

Electronic device and method for controlling device clock frequencies based on detected link information

Embodiments of the present disclosure relate to a storage system and an operating method thereof. According to the embodiments of the present disclosure, the storage system may include N (N is a natural number) temperature sensors and M (M is a natural number of 2 or more) modules, and may determine a thermal throttling level for each of the M modules based on N temperature information pieces collected from the N temperature sensors and N weights corresponding to the N temperature sensors, wherein the N weights are different for each of the M modules, and the storage system may perform the thermal throttling for the M modules based on the thermal throttling levels for the M modules respectively.

Storage system and operating method thereof

An electronic device includes a plurality of cores, and a clock generator configured to provide a plurality of clock signals to the plurality of cores, respectively, wherein the plurality of cores includes a system core that controls the clock generator to generate the clock signals having frequencies of the respective cores, wherein the frequencies are optimized and determined based on a type of an event of the electronic device, and wherein to clock signals with optimized frequencies are applied to the respective cores in order to perform the event.

Growing community of inventors

Icheon-si, South Korea

Ku Ik Kwon