Nxp Usa, Inc.

Freescale Semiocnductor, Inc.

Kshitij Bajaj

Michael Andreas Staudenmaier

Chanpreet Singh

Vincent Aubineau

Sarthak Mittal

Mehul Kumar

Dirk Wendel

Tejbal Prasad

Snehlata Gutgutia

Steven Bruce McAslan

Ritesh Agrawal

Abhineet Kumar Bhojak

Anisha Ladsaria

Nakul Grover

The present application relates to a system for verifying integrity of a stream of image frames including an encoder logic module and a decoder logic module. On source side, a test line insertion logic module receiving the stream is arranged upstream to the encoder logic module encoding the stream. The test line insertion logic module is configured to include one or more test lines into the image frames. A color coding is assigned to the one or more test lines. The color coding is selected from a coding scheme. On destination side, a test line detection and extraction logic module is arranged downstream to the decoder logic module receiving the encoded stream. The test line detection and extraction logic module extracts the color coding from the received image frames and verifies extracted coding data against the coding scheme. The coding data comprises at least the extracted color coding.

System encoder and decoder for verification of image sequence

A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.

Method and apparatus for managing graphics layers within a graphics display component

A display control apparatus comprising at least one memory element within which image data is stored, at least one display controller arranged to read from the, or each, memory element the image data and to output display data generated from the read image data to at least one display device. The display control apparatus further comprises at least one interface component via which the display controller is arranged to read image data from the memory element. The display control apparatus further comprises at least one interface bandwidth control component arranged to measure image data flow over the interface component from the memory element to the display controller, and configure a bandwidth for image data flow over the interface component from the memory element to the display controller based at least partly on the measured image data flow.

Display control apparatus and method of configuring an interface bandwidth for image data flow

A diagnostic data generation apparatus for a display controller comprises an underrun detector arranged to monitor, when in use, buffer depletion in order to detect an underrun condition. The underrun condition results from a data feed lag associated with a mismatch between a buffer fill rate and a predetermined output data rate. The underrun detector is arranged to generate diagnostic data in response to detection of the underrun condition, the diagnostic data identifying the underrun condition and a location in an array of pixels associated with the underrun condition.

Diagnostic data generation apparatus, integrated circuit and method of generating diagnostic data

A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to:

Head-up display warping controller

A display control unit is connected to a display and arranged to generate a video signal representing a sequence of video frames to be displayed consecutively on said display. The display control unit may include a first memory unit arranged to buffer a set of image descriptors; a second memory unit connected between said first memory unit and said display; an update unit connected to said first memory unit and arranged to update said image descriptors in said first memory unit and to generate a proceed signal only when said set of image descriptors in said first memory unit is up to date; a copy unit arranged to copy said image descriptors from said first memory unit to said second memory unit in response to said proceed signal; and a video unit arranged to generate said video signal on the basis of said image descriptors in said second memory unit.

Display control unit and method for generating a video signal

The present application relates to a display controller and display system and a method of operating thereof. At a filtering stage display image data are generated on the basis of received pixel-mapped image data. The filtering operation accepts a plurality of pixels out of the received image data as input values to generate a pixel of the display image data as output value. It is further determined whether the plurality of pixels being the input values to the filtering operation are marked. If all pixels thereof are marked, the output pixel being the output value is marked. The marked pixels in the display image data are validated on the basis reference data.

Display controller, heads-up image display system and method thereof

An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.

Asynchronous FIFO buffer with Johnson code write pointer

A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.

Growing community of inventors

Sirsa, India

Kshitij Bajaj