Infineon Technologies Ag

Intel Corporation

Krzysztof Domanski

Cornelius Christian Russ

Kai Esmark

David Alvarez

Wolfgang Soldner

Harald Gossner

Christian Cornelius Russ

Gernot Langguth

Klaus Von Arnim

Adrien Benoit Ille

David Johnsson

Stephan Henzler

Jens Schneider

Heike Schwager

Stephan Drueen

Benjamin J Orr

Jenia Elkind

Angelika Jungmann

A circuit for electrostatic discharge (ESD) protection for wide frequency range multi-band interfaces. The interface may be split into a plurality of signal paths. Each signal path may include an ESD protection circuit configured to shunt an ESD current on each signal path to either ground or supply voltage and a filter configured to block signals from other signal paths. The signal paths are connected to a common signal line such that the signals for the plurality of signal paths can be transported simultaneously. The plurality of signal paths may be a high frequency path and a low frequency path. The low frequency path may include an inductor connected in series and the high frequency path may include a capacitor or transformer connected in series. The ESD protection circuit on each signal path is placed behind the inductor, the capacitor or the transformer.

Circuit for electrostatic discharge protection for wide frequency range multi-band interfaces

An apparatus is described. The apparatus includes an electronic circuit includes multiple supply voltage nodes, an output node and an internal node. The electronic circuit also includes first protection circuitry coupled between the internal node and the output node. The electronic circuit also includes a control circuit coupled to the internal node to bias the internal node. The electronic circuit also includes second protection circuitry coupled to the internal node.

Multi-level output circuit having centralized ESD protection

A directional pulse injection system and method are described for injecting a pulse into a microelectronic system for electrostatic test. One example has a transformer coupled to a pulse source through a transmission line and to a conductive trace of a test board to apply the electrical pulse to the trace as a test pulse. The test board is connected to a microelectronic device under test. This example also has a cancellation pulse transmission line coupled to the pulse source and a cancellation pulse contact coupled to the pulse source through the cancellation pulse transmission line and to the trace on a side of the trace opposite the transformer to receive a cancellation signal from the pulse source and to couple the cancellation signal to the trace to cancel a portion of the test pulse.

Directional pulse injection into a microelectronic system for electrostatic test

In accordance with an embodiment, an integrated circuit has a first transistor made of a plurality of first transistor segments disposed in a well area, and a second transistor made of at least one second transistor segment. Drain regions of the plurality of first transistor segments and the at least one second transistor segment are coupled to a common output node. The at least one second transistor segment is disposed in the well area such that an electrostatic discharge pulse applied to a common output node homogenously triggers parasitic bipolar devices coupled to each drain region of the plurality of first transistor segments and the drain region of the at least one second transistor segment.

System and method for an integrated circuit having transistor segments

In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Semiconductor ESD circuit and method

Implementations are presented herein that include an ESD protection structure. The structure may include a plurality of first doped regions forming first terminals of a plurality of transistors, a plurality of second doped regions forming second terminals of the plurality of transistors, and a third doped region surrounding the plurality of first doped regions and the plurality of second doped regions to form a common third terminal of the plurality of transistors. The plurality of first doped regions and the plurality of second doped regions may be arranged in an alternating pattern such that an ESD discharge current received on any one of the plurality of first doped regions dissipates through at least two of the plurality of second doped regions.

ESD protection structure, integrated circuit and semiconductor device

A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Semiconductor ESD device and method of making same

Devices, semiconductor structures and methods are provided, where a substrate is around a semiconductor device is biased via a resistive element.

Semiconductor devices and structures

Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.

Electrostatic discharge clamping devices with tracing circuitry

Devices and methods are provided, wherein a diode string is provided in a well and the well is biased with an intermediate voltage between voltages applied to terminals of the diode string.

Diode string

Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.

Electrostatic discharge blocking circuits

Method of forming a semiconductor device including a silicon controlled rectifier

An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.

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Munich, Germany

Krzysztof Domanski