Texas Instruments Corporation

Krunali T Patel

David W Rekeita

David W Rekieta

Mark A Beadle

David E Dickens

Chen Ding

A controller ( ) for coupling between a computer bus ( ) and one or more units ( ) compatible with the bus. The controller comprises a first input ( ) for receiving a first reset signal issued from the computer bus, and a second input ( ) for receiving a second reset signal. The controller further comprises circuitry ( ) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry ( ) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.

Circuits, systems, and methods for efficient wake up of peripheral component interconnect controller

The method of the present invention includes maintaining a first tier and a second tier of devices that have access to a secondary bus that a PCI to PCI bridge services. Each device that has access to secondary PCI bus is categorized into either first tier or a second tier . The devices in first tier are provided more frequent opportunities to gain access to secondary PCI bus than devices in low tier . Next, a pending transaction is recognized when an initiating device that has been categorized into second tier accesses secondary PCI bus and attempts a transaction that crosses PCI to PCI bridge to primary PCI bus . However, PCI to PCI bridge is unable to complete the transaction on primary PCI bus . Therefore, PCI to PCI bridge is unable to provide access to any other device on secondary bus until the pending transaction completes. Next, device that initiated the pending transaction is categorized into first tier until the pending transaction is completed.

Method and apparatus for multiple tier intelligent bus arbitration on a PCI to PCI bridge

A method and apparatus for intelligent configuration register access on a PCI to PCI bridge (,) are provided. A read to configuration information of a connected PCI device (,) is identified. It is then determined whether the connected PCI device (,) is one for which the read should be trapped. If the read should not be trapped, the read is passed on to the connected PCI device (,). If the read should be trapped, the type of PCI device is determined for the connected PCI device (,). Data is then returned representing the configuration information in a format appropriate for the type of PCI device. In one aspect, the configuration information comprises the subsystem ID and subsystem vendor ID of the PCI device.

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Allen, TX, United States of America

Krunali T Patel