Xilinx, Inc.

Kristof Denolf

Kornelis Antonius Vissers

Jack S Lo

Ralph D Wittig

Eric F Dellinger

Michaela Blott

Nicholas Fraser

Zachary Blair

Yaman Umuroglu

Louis Coulon

Alireza Khodamoradi

A method for operating a computing system includes determining a baseline accuracy of the computing system based on a baseline data transmission format comprising a baseline quantity of data bits and a baseline quantity of error correction (ECC) bits, determining sample accuracies of the computing system based on sample data transmission formats each including a quantity of data bits and a quantity of ECC bits that are different from the baseline quantity of data bits and the baseline quantity of ECC bits, and storing data in a memory device of the computing system using at least one data transmission format, wherein the at least one data transmission format is selected from a group of data transmission formats comprising the baseline data transmission format and the sample data transmission formats and the at least one data transmission is selected based on the baseline accuracy and the sample accuracies.

Reclamation of memory ECC bits for error tolerant number formats

Embodiments herein describe a learnable transform block disposed before, or in between, the neural network layers to transform received data into a more computational-friendly domain while preserving discriminative features required for the neural network to generate accurate results. In one embodiment, during a training phase, an AI system learns parameters for the transform block that are then used during the inference phase to transform received data into the computational-friendly domain that has a reduced size input. The transformed data may require less compute resources or less memory usage to process by the underlying hardware device that hosts the neural network.

Implementation-tuned architecture for neural network processing in a learned transform domain

An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.

Learning neural networks of programmable device blocks directly with backpropagation

A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Circular buffer architecture using local memories with limited resources

An example a method of optimizing a neural network having a plurality of layers includes: obtaining an architecture constraint for circuitry of an inference platform that implements the neural network; training the neural network on a training platform to generate network parameters and feature maps for the plurality of layers; and constraining the network parameters, the feature maps, or both based on the architecture constraint.

Architecture optimized training of neural networks

An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.

Data mover circuitry for N-dimensional data in an integrated circuit

Digital signal processing and, more particularly, digital video coding is described. Video encoding or decoding of frames includes accessing a plurality of values that can include at least one quantized DC default value and a plurality of quantized DC block values for neighboring blocks with respect to an intra block. A direction of change for the intra block is determined using predictor values obtained from the accessed values.

Digital video coding using quantized DC block values

Methods and devices for encoding and decoding video data are provided, wherein an image data structure can be represented as a group of macroblocks and each macroblock contains a plurality of blocks. One inventive aspect includes a method of decoding image data comprises decoding a current block of data, comprising retrieving a related reference block, decoding texture information of the current block, and reconstructing the current block, prior to the decoding of another block of data.

Growing community of inventors

Longmont, CO, United States of America

Kristof Denolf