Intel Corporation

Tahoe Research, Ltd.

Santa Clara

Kristof Darmawikarta

Robert Alan May

Sri Ranga Sai Boyapati

Srinivas V Pietambaram

Aleksandar Aleksov

Hiroki Tanaka

Rahul N Manepalli

Sameer Paital

Jeremy D Ecton

Bai Nie

Islam A Salama

Yonggang Li

Brandon C Marin

Gang Duan

Tarek A Ibrahim

Benjamin Duong

Chung Kwang Christopher Tan

Telesphor Kamgaing

Robert L Sankman

Amruthavalli Pallavi Alur

Javier Soto Gonzalez

Andrew James Brown

Prithwish Chatterjee

Jung Kyu Han

Rahul Jain

Sheng C Li

Wei-Lun Kane Jen

Thomas L Sounart

Jesse Jones

Sri Ranga Sai Sai Boyapati

Johanna M Swan

Adel A Elsherbini

Debendra Mallik

Henning Braunisch

Suddhasattwa Nad

Steve S Cho

Xiaoying Guo

Changhua Liu

Arnab Sarkar

Srinivas Venkata Ramanuja Pietambaram

Thomas Heaton

Haobo Chen

Ali Lehaf

Kyu Oh Lee

Dilan Seneviratne

Veronica Aleman Strong

Yikang Deng

Amanda E Schuckman

Darko Grujicic

Hongxia Feng

Sashi S Kandanur

Jonathan Rosch

Kwangmo Lim

Feras Eid

Kemal Aygun

Ofir Degani

Zhiguo Qian

Pooya Tadayon

Eyal Fayneh

Chong Zhang

Dingying David Xu

Siddharth K Alur

Lauren Ashley Link

Lilia May

Hari Mahalingam

Rengarajan Shanmugam

Kwangmo Chris Lim

Chung Kwang Tan

Sandeep Gaan

David Levy

Sujit Sharan

Georgios C Dogiamis

Omkar G Karhade

Ravindranath Vithal Mahajan

Nitin A Deshpande

Leonel R Arana

Junnan Zhao

Sai Vadlamani

Sri Chaitra Jyotsna Chavali

Ji Yong Park

Nicholas S Haehn

Mark S Hlad

Daniel N Sobieski

Praneeth Kumar Akkinepally

Frank Truong

Kyle Jordan Arrington

Meizi Jiao

Yosuke Kanaoka

Jason M Gamba

Oscar Ojeda

Matthew L Tingey

Marcel Arlan Wall

Jiwei Sun

Arnab Roy

Mohit Bhatia

Amruthavalli Palla Alur

Roy Dittler

Vahidreza Parichehreh

Arghya Sain

Sri Chaitra Chavali

Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Substrate integrated thin film capacitors using amorphous high-k dielectrics

Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

Glass substrates having transverse capacitors for use with semiconductor packages and related methods

An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.

Glass interposer optical switching device and method

Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Lithographic cavity formation to enable EMIB bump pitch scaling

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Omni directional interconnect with magnetic fillers in mold matrix

The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

Optimization for raster scanning

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.

Die last and waveguide last architecture for silicon photonic packaging

Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a through glass via (TGV). The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

Glass substrates having signal shielding for use with semiconductor packages and related methods

Embodiments described herein relate to lithographically defined vertical interconnect accesses (litho-vias) for a bridge die first level interconnect (FLI) and techniques of fabricating such litho-vias. In one example, a package substrate comprises a bridge die embedded in the package substrate; a first contact pad outside a perimeter of the bridge die; a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via; a third pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via. The first contact pad has a surface finish disposed thereon. A first protruded interconnect structure is positioned on the first via and a second protruded interconnect structure is positioned on the second via. Each of the first and second vias have sidewalls that are substantially vertical.

Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI)

Glass interposer optical resonator device and method

A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

Inorganic-based embedded-die layers for modular semiconductive devices

An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

Coreless electronic substrates having embedded inductors

Growing community of inventors

Chandler, AZ, United States of America

Kristof Darmawikarta