Cypress Semiconductor Corporation

Longitude Flash Memory Solutions Ltd.

Infineon Technologies LLC

Other

Cypress Semiconductor Corportion

Cypress Semiconductor Company

Krishnaswamy Ramkumar

Sagy Charel Levy

Fredrick B Jenne

Igor Polishchuk

Venkatraman Prabhakar

Jeong Soo Byun

Alain Paul Blosse

Sam G Geha

Sundar Narayanan

Igor G Kouznetsov

Ravindra Manohar Kapre

Mira Ben-Tzur

Bo Jin

Sharmin Sadoughi

Frederick B Jenne

Long Hinh

Vineet Agrawal

Santanu Kumar Samanta

Hanna Bamnolker

Manuj Rathor

Ali Keshavarzi

James A Hunter

Thurman John Rodgers

William W C Koutny, Jr

William Koutny

Swatilekha Saha

Michael Amundson

Fuad Badrieh

Maroun Khoury

Loren T Lancaster

Kaichiu Wong

Mike Bruner

Pamela Shiell Trammel

Prabhuram Gopalan

Jeremy L Warren

Biju Parameshwaran

Chidambaram G Kallingal

Venkataraman Prabhakar

Hui-Mei Shih

Steven Hedayati

James Montague Cleeves

Dafna Beery

Shan Sun

Lei Xue

Rinji Sugino

Suraj Puri

Raj Mohindra

Rajiv Bhushan

Shivananda Shetty

Peter H Voss

Thomas Davenport

Kedar Patel

Gorley L Lau

Shahin Sharifzadeh

Xiaojun Yu

Christopher A Seams

Yitzhak Gilboa

David C Wong

Fred B Jenne

Michal Efrati Fastow

Venuka K Jayatilaka

Chan Lon Yang

Yu Yang

Saurabu Dutta Chowdhury

Sang S Kim

Avner Shelem

Gary Elmore

Hui-Mei (Mei) Shih

Michael Allen

Gary Menezes

Klyoko Ikeuchi

Seurabh Dutta Chowdhury

Renhua Zhang

Klyoko Keuchi

Sriram Madhavan

An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Nonvolatile charge trap memory device having a high dielectric constant blocking region

A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

Oxide-nitride-oxide stack having multiple oxynitride layers

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Methods of equalizing gate heights in embedded non-volatile memory on HKMG technology

A fabrication method of a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in-situ atomic layer deposition (ALD) tool or chamber. Radical oxidation or oxide deposition process steps are performed to form tunnel dielectric layer overlying the substrate. Silicon nitride deposition process steps are also performed to form a multi-layer charge trapping (CT) layer in which at least some of the process parameters of silicon nitride deposition process steps are adjusted when forming the first and second CT sub-layers of the multi-layer CT layer. Subsequently, radical oxidation or oxide deposition process steps are performed in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer.

Method of forming oxide-nitride-oxide stack of non-volatile memory and integration to CMOS process flow

A method of operating a semiconductor inference device that includes the steps of writing one of multiple analog weight values to memory cells of a non-volatile memory (NVM) array, receiving inputs through a bus system, performing multiply accumulate (MAC) operations based on the inputs and the stored analog weight values, converting results of the MAC operations to outputs, and transmitting the outputs through the bus system.

Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Method of ono integration into logic CMOS flow

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Memory transistor with multiple charge storing layers and a high work function gate electrode

A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N&#xd7;analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof

An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a non-volatile memory (NVM) transistor including a charge-trapping layer and a blocking dielectric, a field-effect transistor (FET) of a first type including a first gate dielectric having a first thickness, a FET of a second type including a second gate dielectric having a second thickness, and a FET of a third type including a third gate dielectric having a third thickness. In some embodiments, the first, second, and third gate dielectric includes a high dielectric constant (high-K) dielectric layer, and the first thickness is greater than the second thickness, the second thickness is greater than the third thickness. Other embodiments are also described.

Embedded sonos with a high-K metal gate and manufacturing methods of the same

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor. The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Embedded SONOS and high voltage select gate with a high-K metal gate and manufacturing methods of the same

A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N&#xd7;analog values corresponding to N&#xd7;levels of its drain current (ID) or threshold voltage (VT) levels, representing N&#xd7;weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.

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San Jose, CA, United States of America

Krishnaswamy Ramkumar