At+t Corp.

At&t Bell Laboratories

American Telephone and Telegraph, Co.

Krishnaswamy Nagaraj

Reza S Shariatdoust

Robert William Walden

Stephen H Lewis

A bandgap voltage generator using a simple bandgap voltage reference supply circuit which has virtually no power supply rejection ratio (PSRR) which can produce an output bandgap voltage, V.sub.BG, using an extremely low power supply voltage, V.sub.DD. In order to increase the PSRR, a signal generated by the bandgap voltage reference supply circuit is amplified by a high gain amplifier circuit comprised of two cascode connected FETs. The highly amplified signal generated by the high gain amplifier circuit drives a voltage regulator, comprised of an FET used as a voltage controlled current sink, which regulates the voltage supplied from the power supply, V.sub.DD, to the bandgap voltage reference supply circuit. This combination of a bandgap voltage reference with virtually no PSRR and a high gain amplifier results in a bandgap voltage generator with a very high PSRR.

Bandgap voltage reference generator

A demodulator circuit receives an input signal read from a track of a magnetic medium and generates a control signal to maintain alignment of a read-write head with the track. The demodulator circuit includes at least one transistor. The at least one transistor has an electrode switchable between first and second voltage sources. The electrode is coupled to the second voltage source to block processing of the input signal. The electrode is coupled to the first voltage source to process the input signal. The at least one transistor provides an effective resistance when coupled to the first voltage source that is dependent on the voltage level of the first voltage source. The at least one transistor half-wave rectifies the input signal when the electrode is coupled to the first voltage source. In this manner, the at least one transistor provides an effective resistance when the electrode is coupled to the first voltage source, the magnitude of the effective resistance being determined by the voltage level of the first voltage source, half-wave rectifies the input signal, and simultaneously selects that portion of the input signal to rectify. Disk drive systems that utilize this technique have the advantage of at least one transistor simultaneously selecting the number of pulses to be integrated when turned on and blocking integration of the input signal when turned off, controlling the gain of an integrator by varying the resistance when turned on, and half-wave rectifying the incoming signal to vary the automatic gain control.

Demodulator circuit

A circuit which detects the median peak of a burst of pulses. The peak value of each pulse in a pulse burst is detected and stored. The peak value of each pulse is then compared to the peak value of every other pulse and the results of the comparison are used to determined the median peak.

Median peak detector for controlling disk pickup head

Control voltages are generated so that each transistor in a plurality of parallel connected field effect transistors turns ON with smooth transitions between transistors and in a manner that is relatively insensitive to processing and operating temperature variations.

Multiple control voltage generation for MOSFET resistors

The median value of a set of voltage values is found by a technique that minimizes the circuitry while maximizing the speed, and also provides for dropouts. The voltage values, illustratively five in number, are applied in pairs to the inputs of ten comparators. The outputs of the comparators, and their complements, are formed into five 'status words' of four bits each, such that each bit of a given status word represents the comparison of a given value with another of the values. The status word that contains two 1's and two 0's represents the median value. In a preferred circuit embodiment, this status word is rapidly determined in a series of three logic stages, wherein the highest and lowest values are eliminated in the first stage, the next highest and lowest are eliminated in the second stage, and the last stage determines the remaining status word that is associated with the median value. This technique also readily provides for dropouts by initializing the logic circuitry. For example, the fifth status word (associated with the fifth value) is preset to 1111, so that if any single value is not received, the missing value is not chosen as the median. Additional dropouts may be similarly treated to ensure that the median is chosen only from the voltage values actually received. This technique may be used, for example, in a disk drive system, where the position of a servo head must be precisely controlled.

Median value detection technique

A cyclic analog-to-digital converter includes two arithmetic circuits and a single comparator. The output of each arithmetic circuit is connected to the input of the other arithmetic circuit. Each arithmetic circuit can modify the analog signal being converted in accordance with output signals from the comparator. Embodiments are disclosed in which the arithmetic circuits include switched capacitors and separate or shared operational amplifiers.

Cyclic analog-to-digital converter

A method and apparatus for improving the performance of a phase-locked loop are disclosed. A phase error between two signals is sensed and a temporary increase in the bandwidth of the phase-locked loop is provided responsive to the sensed phase error. The phase-locked loop may comprise a charge pump and the temporary increase in the bandwidth of the phase-locked loop may comprise a temporary increase in charge pump current. An increase in phase-locked loop bandwidth is followed by a decrease in the bandwidth responsive to a decrease in phase error. The decrease in bandwidth may comprise a decrease in charge pump current.

Adaptive charge pump for phase-locked loops

A class AB CMOS amplifier stage is disclosed having well-controlled low quiescent current and good phase stability. A first FET in a complementary push-pull output stage is driven directly by an input signal biased so that such FET conducts a small quiescent current. The second FET in the output stage is driven through a level shifting circuit. The quiescent current in the level-shifting circuit is controlled by a reference voltage. The FETs in the output stage, the level-shifting circuit and the reference-voltage generator are sized with respect to each other to determine the relative magnitudes of quiescent currents and the overall gain of the circuit. The operation of the circuit is essentially independent of process-induced variables and power-supply fluctuations. The FETs in the level-shifting stage can have relatively low impedances for good phase response property.

Class AB CMOS amplifier

A switched capacitor circuit with a very large time constant. Numerous low frequency analog applications, modems for example, require this type of circuit. The capacitances required to obtain a sufficiently large time constant are reduced over prior art techniques by as much as 50%. The circuit is insensitive to parasitic capacitances. The circuit comprises a switched input sampling capacitor, an operational amplifier and a first feedback capacitor connected in parallel with the amplifier. The switched sampling capacitor samples an input signal in a first clock phase. A second feedback capacitor is switched during the first phase to sample the output of the operational amplifier; and, in a second phase, it is switched in parallel with the first feedback capacitor of the amplifier.

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Macungie, PA, United States of America

Krishnaswamy Nagaraj