Advanced Micro Devices Corporation

Spansion Llc.

Krishnashree Achuthan

Kashmir S Sahota

Sergey D Lopatin

Bin Yu

Haihong Wang

Shibly S Ahmed

Unsoon Kim

Minh Van Ngo

Cyrus E Tabery

Amit P Marathe

Jean Y Yang

Angela Tai Hui

Steven C Avanzino

Yu Nan Sun

Arvind Halliyal

Christy Mei-Chu Woo

Hiroyuki Kinoshita

Dawn M Hopper

Ning Cheng

Yider Wu

Harpreet Kaur Sachar

Jayendra D Bhakta

Jeffrey P Erhardt

Emmanuil Lingunis

Christopher H Raeder

Patrick K Cheung

James J Xie

Jack F Thomas

Christopher Foster

Brad Davis

Patriz C Regalado

According to one exemplary embodiment, a method includes a step of forming a polysilicon layer over a substrate by using a deposition process, where the deposition process causes polysilicon nodule defects to form on a top surface of the polysilicon layer. The method further includes performing a polysilicon CMP process on the polysilicon layer, where the polysilicon CMP process removes a substantial percentage of the polysilicon nodule defects from the top surface of the polysilicon layer. The CMP process removes at least 95.0 percent of the polysilicon nodule defects from the top surface of the polysilicon layer. According to this embodiment, the polysilicon CMP process utilizes a polishing pressure that is less than 1.5 psi. The polysilicon CMP process also utilizes a table speed of between 20.0 rpm and 40.0 rpm. The polysilicon CMP process further utilizes a colloidal silica slurry.

Method for effectively removing polysilicon nodule defects

According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.

Method for decreasing sheet resistivity variations of an interconnect metal layer

A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

Non-critical complementary masking method for poly-1 definition in flash memory device fabrication

According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.

Method for controlling poly 1 thickness and uniformity in a memory array fabrication process

A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial 'rough' planarization and then a 'fine' planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Multi-step chemical mechanical polishing of a gate area in a FinFET

According to one exemplary embodiment, a method of fabricating an array on a substrate includes forming a layer of a first material adjacent to and over a plurality of segments of a second material on the substrate. The method further includes performing a first CMP process step to form a plurality of segments of the first material, where the plurality of segments of the first material alternate with the plurality of segments of the second material. According to this exemplary embodiment, the method further includes performing a second CMP process step to achieve a target thickness of the plurality of segments of the first material. The first CMP process step comprises a first slurry having particles of a first particle size and the second CMP process step comprises a second slurry having particles of a second particle size, where the second particle size is smaller than the first particle size.

Method for reducing edge array erosion in a high-density array

A method of manufacturing a planarized semiconductor wafer in which a semiconductor wafer is provided with a chemical-mechanical polishing stop layer deposited thereon. A photoresist layer is processed and used to form a patterned chemical-mechanical polishing stop layer and shallow trenches. A shallow trench isolation material is then grown on the chemical-mechanical polishing stop layer and in the shallow trenches, and is chemical-mechanical polished to the chemical-mechanical polishing stop layer.

Method for semiconductor wafer planarization by isolation material growth

A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.

Flash memory cell with UV protective layer

A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Dual silicon layer for chemical mechanical polishing planarization

The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.

Tightly spaced gate formation through damascene process

A FinFet-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

Method for semiconductor wafer planarization by CMP stop layer formation

A manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Growing community of inventors

San Ramon, CA, United States of America

Krishnashree Achuthan