General Instrument Corporation

The Titan Corporation

M/a-com Government Systems, Inc.

Krishnanand Kelkar

William A Shumate

Gordon Kent Walker

Franklin Peter Antonio

Steven H Gardner

Daniel Ray Kindred

Steven L Rogers

Thomas C Reiner

Mark J Lindsey

Thomas R Bilotta

A decoding system for decoding a digital data stream that has been convolutionally encoded in accordance with a selected constraint length and selected polynomial codes, which system includes a processor, such as a Viterbi decoder, that is reconfigurable so that it can decode encoded digital data streams for a number of different user channels for which data streams have been convolutionally encoded in accordance with respectively different combinations of selected constraint length and selected polynomial codes. The decoding system includes a Viterbi decoder for processing the encoded data stream in accordance with said selected constraint length and in accordance with said selected polynomial codes to decode the encoded data stream; a RAM for storing data of said selected constraint length and data of said selected polynomial codes in accordance with which said data stream was encoded; and a RAM I/O interface circuit responsive to a user channel identification signal for retrieving said selected constraint length data and said selected polynomial code data from the RAM and configuring the Viterbi decoder in accordance with said selected constraint length and said selected polynomial codes. In order to accommodate concurrent multiple user channels, the RAM stores different sets of combinations of constraint length data and polynomial code data corresponding to different user channels, with said different sets being retrievable from the RAM in response to respectively different user channel identification signals. The polynomial code data and constraint length data in the RAM may be changed from time to time in response to software instructions, as user channel requirements change. The Viterbi decoder processes said encoded data stream over a plurality of decoding cycles and produces intermediate decoding results during different decoding cycles; and the RAM I/O interface circuit stores in the RAM said intermediate decoding results produced for each different user channel during the different decoding cycles.

Reconfigurable, multi-user Viterbi decoder

A video scrambling system scrambles adjacent sequentially odd and even video information lines of a video frame by simultaneously storing in a memory a pair of such adjacent lines; and forming a pair of scrambled video information lines by retrieving from the memory a segment of one of the stored video information lines followed by a segment of the other stored video information line, and by shifting the phase of one of the retrieved segments of the scrambled video information line in relation to the other retrieved segment of said scrambled video information line by an odd multiple of one-half the phase of the chrominance information cycle. This phase shift causes the phase relationship of all segments with respect to the color reference signal to be the same; and as a result there is no differential hue shift in the descrambled signal. In a complementary descrambling system, the two retrieved segments of each descrambled video information line are retrieved consecutively without an intervening phase shift. Security of the scrambled signal against unauthorized descrambling is enhanced by delaying the provision of an encryption keystream to a control unit that sets the cutpoint between the segments in accordance with said keystream, and further using the keystream to set the amount of said delay.

Video scrambling and descrambling by varying sequence of segments in

A decoding system capable of outputting Viterbi-decoding-algorithm-decoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm to produce the decoded data. The system includes a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus. Each of the decoders in the ring includes an input buffer, timing controller, decoding processor and output buffer. The input buffer responds to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data. The timing contoller provides a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder. The decoding processor processes the buffered block of coded data at a given rate to produce decoded data. The output buffer buffers the block of decoded data. The timing controller also responds to a start-up signal provided by a preceding decoder in the ring by causing the buffered decoded data to be provided onto the data output bus at a predetermined rate that is greater than the given rate at which the coded data is processed to produce the decoded data; and further provides a start-output signal to the succeeding decoder in the ring to cause the succeeding decoder to provide a portion of the buffered decoded data therein onto the data output bus at a predetermined rate and at such time as to be continuous from and not overlap the portion of the buffered decoded provided onto the output data bus from the instant said decoder.

Decoder ring system

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San Diego, CA, United States of America

Krishnanand Kelkar