International Business Machines Corporation

Globalfoundries Inc.

Kyndryl, Inc.

Krishnan Sugavanam

Martin Ohmacht

Alan G Gara

Dong Chen

Mark Edwin Giampapa

Peter Boyle

Norman Christ

Valentina Salapura

Philip Heidelberger

Matthias Augustin Blumrich

Bruce Martin Fleischer

Burkhard Steinmacher-Burow

Aris Gkoulalas-Divanis

Thomas Winters Fox

Uri Kartoun

Rudolf Adriaan Haring

Robert Mawhinney

Paul William Coteus

Todd Edward Takken

Shawn Anthony Hall

George L Chiu

Gerard Vincent Kopcsay

Dirk Hoenicke

David L Satterfield

Ashwini K Nanda

Jayanth Krishnan

Ralph E Bellofatto

Sophie Batchelder

Michael K Gschwind

Michael A Blocksome

Joseph D Ratterman

Adam James Muff

Ravi Nair

Hans Mikael Jacobson

Alexandre E Eichenberger

Robert William Wisniewski

Thomas M Gooding

John A Gunnels

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

John Kevin O'Brien

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Craig Brian Stunkel

Douglas R Miller

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Changhoan Kim

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Brant L Knudson

Kahn C Evans

Sandhya Koteshwara

William Maupin Stockdell

Alfred Thomas Watson, Iii

Paul R Bastide

Zachary A Silverstein

Brian E Smith

Steven Michael Douskey

Thomas Mario Cipolla

Ramendra K Sahoo

Dietmar Schmunkamp

Michael Seth Silverstein

Marc B Dombrowa

Moyra Kathleen McManus

Keith Kaplan

Bryan J Weatherford

A computer-implemented method for organizing tasks presented on a graphical user interface of a computer hardware system for a user includes the following operations. An electronic message associated with a collaborative messaging application executing with the computer hardware system is received. A first collaboration having one or more collaborative tasks is identified from the electronic message. A need-for-action, a time-to-act, and a time-to-complete are determined for the first collaboration. A moving average for the first collaboration is adjusted based upon the need-for-action, the time-to-action, and a time-to-complete. The presentation of the first collaboration within the graphical user interface is altered based upon the moving average.

Ordering collaborative actions in a graphical user interface

According to one embodiment, a method, computer system, and computer program product for user authentication. The embodiment may include receiving, at an authentication server, respective multiple location coordinates from first and second registered devices. Storing, on the authentication server, respective moving windows comprising registered, device specific, last n location coordinates from the first and the second registered devices. Receiving a request to access the authentication server via the first registered device. The request comprises log-in credentials of a user and a first hash value calculated at the first registered device. Computing, at the authentication server, a second hash value using a set of the last n location coordinates from each of the respective moving windows. Comparing the first hash value and the second hash value. In response to the first and the second hash values being equal, and the log-in credentials being verified, granting access to the authentication server.

Location coordinate-based user authentication with device loss security tolerance

According to one embodiment, a method, computer system, and computer program product for user authentication. The embodiment may include receiving, from a first device, multiple location coordinates of the first device. The embodiment may include storing, on a second device, a second moving window comprising last n location coordinates of the multiple location coordinates. The embodiment may include receiving, from the first device, a request to access the second device, wherein the request comprises log-in credentials and a first hash value. The embodiment may include computing, on the second device, a second hash value based on the second moving window. The embodiment may include verifying the log-in credentials. The embodiment may include comparing the first hash value and the second hash value. In response to the first and the second hash values being equal, and the log-in credentials being verified, the embodiment may include granting access.

User authentication based on periodic sampling of location coordinates

A method secures a computer display. One or more processors detect whether there is a presence of an authorized portable device proximate to the computer display. Based on what the processor(s) detect, the processor(s) apply a rule, which is based on one or more portable devices being proximate to the computer display, to selectively continue or end a current session on the computer display.

Controlling a display based on a proximity of a portable device

A computer-implemented method for obfuscating sensitive information associated with mail delivery is disclosed. The computer-implemented method includes identifying that a piece of mail directed towards a potential recipient includes a particular type of sensitive information. The computer-implemented method further includes selecting a mail obfuscation policy for the particular type of sensitive information based on the particular type of sensitive information. The computer-implemented method further includes performing an obfuscation action with respect to the particular type of sensitive information based on the selected mail obfuscation policy.

Method for concealing sensitive mail return addresses

A computer-implemented method includes: receiving, by a computing device, text extracted from a webpage in a browser and a Uniform Resource Locator (URL) of a linked webpage associated with the text; generating, by the computing device, questions based on the text; retrieving, by the computing device, content of the linked webpage using the URL; generating, by the computing device, answers to the questions using the retrieved content; and returning, by the computing device, the questions and the answers to the browser such that the browser displays the questions and the answers in the webpage.

Autonomous webpage content summation

Embodiments for managing a computing system are provided. A Root-of-Trust (RoT) device within the computing system is caused to boot. The computing system includes at least one peripheral device, and the RoT device is in operable communication with the at least one peripheral device and a management server. The at least one peripheral device is caused to at least partially boot. The RoT device is caused to retrieve a firmware image associated with the at least one peripheral device from the management server. The at least one peripheral device is caused to reboot utilizing the firmware image.

Methods and systems for creating root-of-trust for computing system components

Described is a baseboard management controller (BMC). The BMC comprises a BMC flash storage storing firmware and an access permission table. The access permission table defines an access control policy for access requests to peripherals communicatively coupled to the BMC. The BMC further comprises an access control chip comprising one or more processors and a write-once memory. The write-once memory stores a copy of the access permission table. The access control chip is configured to manage access to the peripherals using the access permission table.

Access control management of baseboard management controller peripherals

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.

Local bypass for in memory computing

Local bypass in memory computing

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Testing and operating a multiprocessor chip with processor redundancy

A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.

List based prefetch

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

Growing community of inventors

Yorktown Heights, NY, United States of America

Krishnan Sugavanam