Cirrus Logic Inc.

Krishnan Subramoniam

Rajendra Datar

Anand Venkitachalam

John L Melanson

Manoj Shridhar Soman

Dylan Alexander Hester

Jens Puchert

Brian K Straup

Joe Welser

Rahul Singh

Ahsan Habib Chowdhury

James Antone

Daniel Gudmondson

Hua Hong

Brian Frank Bounds

Anad Venkitachalam

Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

Method and apparatus to improve decoding of composite video signals

A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.

Method and system for providing a codec clock signal at a desired operational rate

A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.

Gain or input volume controller and method utilizing a modified R2R ladder network

A current steering digital to analog converter includes a current source for selectively providing a selected amount of current to an output in response to input data. The current source includes a selected number of sub-current sources for selectively providing fractions of the selected amount of current to the output. Compensation current sources each provide a selected amount of compensation current to the output. Compensation control circuitry, in response to the input data, selectively activates and de-activates selected ones of the sub-current sources and the compensation current sources to provide current compensation at the output.

Current steering digital to analog converters with self-calibration, and systems and methods using the same

A system and method of operating a codec in an operational mode are disclosed. The codec is operated in a digital centric mode. The digital centric mode involves the following: An analog mixer of the codec first mixes analog signals, if any, to produce a mixed analog signal. An analog-to-digital converter converts the mixed analog signal into a converted digital signal. A digital mixer mixes the converted digital signal with digital signals that are otherwise generally unavailable as analog signals to the codec without additional conversions to produce a mixed digital signal. A digital-to-analog converter converts the mixed digital signal into a mixed analog signal. A digital processor may perform digital effects processing on the mixed digital signal to add digital effects to the mixed digital signal. The codec is still able to alternatively operate in an analog centric mode, a host processing mode, or a multi-channel mode.

Method and system of operating a codec in an operational mode

A method of performing sample rate conversion in a data converter operating from an oversampling clock corresponding to a native sample rate and a native oversampling factor. A virtual sample rate and a virtual oversampling factor are selected proportional to the native sample rate and the native oversampling factor. A data stream having a data sample rate is sampled by the virtual oversampling factor. The data stream is also resampled with a resampling ratio approximating a ratio of the data sample rate to the virtual sample rate.

Sample rate converters using virtual sample rates and analog to digital and digital to analog converters using the same

An integrated analog to digital and sample rate converter includes sampling circuitry for receiving an analog signal and generating a single or multibit stream of digital signals at a first rate. A leaky integrator filter removes quantization noise from the stream of samples such that resampling can be carried out. Circuitry resamples the filtered stream of samples output from leaky integrator filter to generate an output stream of samples at a second rate.

Analog to digital converters with integral sample rate conversion and systems and methods using the same

A sample rate converter for converting a data stream having a first base sampling frequency to a data stream having a second base sampling frequency. Up-sampling circuitry receives first oversampled data having a first oversampling ratio with respects to the first base frequency and outputs second oversampled data having a second oversampling ratio with respects to the first base sampling frequency. Resampling circuitry resamples the second oversampled data by a resampling frequency ratio of integers representing a ratio of the first and second base frequencies and generates third oversampled data having the second oversampling ratio with respects to the second base frequency. Down-sampling circuitry then down-samples the third oversampled data and generates fourth oversampled data having the first oversampling ratio with respects to the second base frequency.

Sample rate converters with minimal conversion error and analog to digital and digital to analog converters using the same

A sample rate converter includes a filter for processing digital data in response to a clock controlled by a clock enable signal, the filter receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.

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Austin, TX, United States of America

Krishnan Subramoniam