International Business Machines Corporation

Globalfoundries Inc.

Texas Instruments Corporation

Marvell Asia Pte., Ltd.

Marvell International Limited

Globalfoundries U.S. Inc.

Krishnan Santhana Rengarajan

Venkatraghavan Bringivijayaraghavan

Dhani Reddy Sreenivasula Reddy

Eswararao Potladhurthi

Dinesh Chandra

George Maria Braceras

Toshiaki Kirihata

Igor Arsovski

Pankaj Agarwal

Vaibhav A Ruparelia

Navin Agarwal

Ramesh Raghavan

Balaji Jayaraman

Rajesh Reddy Tummuru

Thejas Kempanna

Nisha Padattil Kuliyampattil

Alok Chandra

Chethan Ramanna

Shiju K Kandiyil

John Maxwell Cohn

Samuel Scott Adams

Darren Lane Anand

Suparna Bhattacharya

Gary Paul Noble

Rashmi Sachan

Janakiraman Viraraghavan

Deepal Wehella-Gamage

Rahul Nayak

Jay M Shah

Arjun Sankar

Sreenivasula Reddy Dhani Reddy

Veena Prabhu

Binu Jose

Sheikh Sabiq Chishti

Abdul M J Muthalif

Madhu Raghava

Panduga Shiva Shankar Reddy

Aditya S Auyisetty

Prasad S Nalawade

Vaibhav V Prabhu

Disclosed is a flip-flop (FF) (e.g., a D-type flip-flop (DFF) or a scan flip-flop (SFF)). The FF is configured to reduce dynamic power consumption of an integrated circuit (IC) by employing only a single-phase of a clock signal. Specifically, the FF includes a primary latch and a secondary latch. Each of these latches includes a multi-stage input driver, which internally generates a control signal based on both the single-phase clock signal and an input signal and which also generates a stored bit signal based on the control signal. Each of these latches can also include a feedback path with an inverter that inverts the stored bit signal and a tri-state logic device that generates a feedback signal that is dependent on the inverted stored bit signal, the control signal and the clock signal. As a result, the FF is a fully digital, static, true single-phase clock (TSPC) flip-flop.

Fully digital, static, true single-phase clock (TSPC) flip-flop

An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Tunable negative bitline write assist and boost attenuation circuit

A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.

Feed forward equalizer with power-optimized distributed arithmetic architecture and method

Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).

Low-power scan flip-flop

A scoped search engine is disclosed. The scoped search engine includes a memory unit storing reference data records. The scoped search engine also includes a data comparison unit that searches the reference data records using different searches. The scoped search engine further includes a match analysis unit that combines result data from the different searches and determines a scope for a subsequent search based on the combined result data.

Scoped search engine

Disclosed is a power-optimized distributed arithmetic (DA)-based feed forward equalizer (FFE) that performs on-demand equalization processing of a data sample. Specifically, a data stream is represented by digital words, which indicate signal levels at taps on a transmission medium. A screener applies formulas to selected taps as opposed to all taps (e.g., to the main cursor tap, which corresponds to the current data sample, and to specific pre-cursor and post-cursor taps, which correspond to immediately proceeding and following data samples) to determine whether the current data sample (which should indicate a specific two-bit symbol) has degraded during transmission to a point where equalization processing is required. If so, a bypass flag is set to a first level so that the data sample is subjected to equalization processing. If not, the bypass flag is set to a second level so that such processing is bypassed. Also disclosed is a corresponding method.

On-demand feed forward equalizer with distributed arithmetic architecture and method

Tunable negative bit line write assist and boost attenuation circuit

A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.

Minimization of bias temperature instability (BTI) degradation in circuits

Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.

Disturb free bitcell and array

Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a Static Random Access Memory (SRAM) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation. The first voltage potential is different than the second voltage potential.

Circuit to improve SRAM stability

Growing community of inventors

Bengaluru, India

Krishnan Santhana Rengarajan