Intel Corporation

Krishnan Ravichandran

Harish Krishnamurthy

Lilly Huang

Vivek K De

Vaibhav Vaidya

Wayne Proefrock

Xiaosen Liu

Khondker Z Ahmed

Sriram R Vangal

Christopher Schaef

Nachiket Venkappayya Desai

Suhwan Kim

Turbo Majumder

Pavan Kumar

Kevin X Zhang

Alexander Uan-Zo-Li

Tomm Aldridge

Rinkle Jain

Scott Chiu

Bradley Saunders

George Matthew

Sheldon Weng

Micah Barany

Bob Jackson

Claudia Patricia Barrera Gonzalez

Jing Han

Rajasekhara Madhusudan Narayana Bhatla

Naoki Matsumura

Willem M Beltman

Andrew Keates

Xia Dai

Suresh K Marisetty

Jessica Gullbrand

Annabelle Pratt

Raviprakash Nagaraj

Stephen Kim

Hee-Jun Park

Gene A Frederiksen

Karthik Sankaranarayanan

Frank K Welch, Jr

Xun Sun

Sunghyun Park

Bernd Nordhausen

John G Tompkins

Suvankar Biswas

Wayne L Proefrock

Frank K Welch Jr

A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.

Computational current sensor

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.

Variable-adaptive integrated computational digital low dropout regulator

A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

Non-linear clamp strength tuning method and apparatus

Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

Multiple output voltage conversion

In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.

Energy harvester with multiple-input multiple-output switched-capacitor (MIMOSC) circuitry

Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

Physically unclonable function implemented with spin orbit coupling based magnetic memory

Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

Peak-delivered-power circuit for a voltage regulator

An electronic device may include a battery charger and a controller. The battery charger may receive a voltage from an energy source, and may provide an output power. The controller may receive a voltage value of the energy source, may receive a current value from the battery charger or the energy source, may determine a power value based on the received voltage value and the received current value, and may provide at least one control signal to the battery charger to change the output power of the charger.

Control of output power of a battery charger for charging a battery of an electronic device from an energy source

Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

Master-slave controller architecture

A system for increasing the life of a battery cell by limiting the charging of the battery to less than full charge in response to a predicted electricity draw of a connected device being less than the full capacity of the battery before a predicted recharge will occur. The current draw of the connected device may be affected by the amount of time before a next recharge and environmental factors. The system may further comprise one or more sensors to gather data pertaining to environmental conditions that may be used in the calculation of a charge termination value. The charge termination value is an amount of charge to power the device for a duration of time at least until a predicted recharge begins.

Systems and methods for adaptive charge termination

Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage having a value based on a value of the first voltage, a first loop to provide digital control information to control a switching of the power switching unit in order to maintain a relationship between the value of the second voltage and a value of a reference voltage, and a second loop coupled to the power switching unit and the first loop to calculate a value of energy consumption of at least a portion of the apparatus based at least on the digital control information.

Digital low drop-out voltage controller including embedded dual-loop feedback for minimum energy point operation

Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, I. The difference between Vin and Vsw represents the maximum inductor current.

Digitally controlled zero voltage switching

In embodiments, apparatuses, methods and systems associated with battery charging are disclosed herein. In various embodiments, a reference current selector may receive a battery voltage sense input and output a reference current level signal, a power point check detector may receive a power supply sense input and output a power point check signal, and a controller coupled to the reference current selector and the power point check detector may receive a battery current sense input and switch a control output based at least in part on the reference current level signal, the battery current sense input, and the power point check signal. Other embodiments may be described and/or claimed.

Battery charging method and apparatus with power point check and switchable control

Growing community of inventors

Saratoga, CA, United States of America

Krishnan Ravichandran