Intel Corporation

Inter Corporation

Krishnamurthy Soumyanath

Ashoke Ravi

Ram K Krishnamurthy

Mark A Anders

Vivek K De

Hasnain Lakdawala

Atila Alvandpour

Frank Patrick O'Mahony

Gaurab Banerjee

Siva G Narendra

Shekhar Yeshwant Borkar

Peter Hazucha

Georgios Yorgos Palaskas

Luiz M Franca-Neto

Richard B Nicholls

Mostafa Elmala

Jeyanandh K Paramesh

Stefan H Andersson

Per Larsson-Edefors

Sanu K Mathew

Dinesh Somasekhar

Tanay Karnik

Stewart S Taylor

Ali Keshavarzi

Hiroyuki Ito

Ganesh Balamurugan

Masoud Sajadieh

Marian K Verhelst

Yorgos Palaskas

Ram Kumar Krishnamurthy

Ravi Naiknaware

Ahmed Biyabani

Jeyanandh Paramesh

Briefly, in accordance with one or more embodiments, a radio device comprises an analog front end comprising a radio to transmit and/or receive radio-frequency signals, and a programmable engine coupled to the analog front end. The programmable engine is capable of being programmed to perform one or more tests on the analog front end and includes a reconfigurable data path reconfigurable by the programmable engine to perform one or more tests on the analog front end.

Programmable engine having a reconfigurable accelerator data path for testing and calibration of analog front ends in radio devices

Architectures including digital outphasing transmitters. Digital signal generation circuitry generates at least two base-band sinusoid signals. Bandpass modulation circuitry is coupled to receive the base-band sinusoid signals and generates at least two modulated digital signals. Power amplifiers are coupled to receive the modulated digital signals to amplify the modulated digital signals. The amplified modulated signals are combined and transmitted.

Digital outphasing transmitter architecture

Disclosed is a system and method for controlling a resonance frequency of a Film Bulk Acoustic Resonator (FBAR) device. The system includes at least one switching capacitor coupled to the FBAR device and a modulator. The at least one switching capacitor includes at least one capacitor and a switch configuration disposed in series with the FBAR device and the at least one capacitor, which is switch configuration capable of opening and closing connection of the at least one capacitor with the FBAR device. The modulator is coupled to the switch configuration, which generates a switching condition signal based on the manufacturing variation in the FBAR device and the environmental effects on the FBAR device. The switch configuration performs opening and closing of the connection of the at least one capacitor and the FBAR device based on the switching condition signal.

System and method for controlling resonance frequency of film bulk acoustic resonator devices

Embodiments of a multicarrier transmitter and method of generating an RF signal for transmission are generally described herein. Other embodiments may be described and claimed. In some embodiments, a multicarrier transmitter generates RF signals for transmission using non-linear switching power amplifiers to amplify outphased switching waveforms allowing the multicarrier transmitter to operate more efficiently than some conventional multicarrier transmitters.

Digital transmitter and methods of generating radio-frequency signals using time-domain outphasing

A discrete time filter achieves gain by sampling a signal using capacitors arranged in a one configuration and then changing the capacitors to a series configuration to develop a filter output voltage. In at least one embodiment, a variable gain filter is achieved by varying the number of capacitors that are active in the filter.

Discrete time filter having gain for digital sampling receivers

A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Low loss interconnect structure for use in microelectronic circuits

Phase and amplitude offsets of a multicarrier transceiver may be reduced by measuring receiver amplitude and phase mismatches of receiver radio-frequency (RF) circuitry by performing a fast Fourier transform (FFT) on a receiver calibration signal.

Transceiver with calibrated I and Q paths and methods for deconvolved calibration

Embodiments of a filter with gain are presented herein.

Filter with gain

The invention concerns 2-oxo-1-pyrrolidine derivatives and a process for preparing them and their uses. The invention also concerns a process for preparing &#x3b1;-ethyl-2-oxo-1-pyrrolidine acetamide derivatives from unsaturated 2-oxo-1-pyrrolidine derivatives. Particularly the invention concerns novel intermediates and their use in methods for the preparation of S-&#x3b1;-ethyl-2oxo-1-pyrrolidine acetamide.

Method and apparatus to combine radio frequency signals

A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Single event upset hardened latch

Techniques to provide DC-offset correction in a variable gain amplifier are described.

Variable gain amplifier with direct current offset correction

Briefly, exemplary embodiments of the invention may provide devices and methods to provide precise and/or low phase-noise quadrature oscillation signals. A quadrature oscillator in accordance with an exemplary embodiment of the invention may include, for example, a phase-shift generator to provide a phase-shift of substantially &#x3c0;/2 radians to an oscillation signal between a first oscillation tank, which provides substantially no phase-shift, and a second oscillation tank.

Quadrature oscillator and methods thereof

A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.

Adaptively extending tunable range of frequency in a closed loop

Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected configurations that take advantage of leakage currents through the FETs so that long resistors or large capacitors are not necessarily required. One embodiment comprises two diode-connected FETs to provide an unbiased DC offset voltage of an analog input signal.

Area efficient waveform evaluation and DC offset cancellation circuits

A strained-silicon voltage controlled oscillator (VCO) includes a first p-channel metal oxide semiconductor (PMOS) device having a strained-silicon layer coupled to a second PMOS device having a strained-silicon layer.

Growing community of inventors

Portland, OR, United States of America

Krishnamurthy Soumyanath