Sandisk Technologies Inc.

Krishnamurthy Dhakshinamurthy

Narendhiran Chinnaanangur Ravimohan

Rajeev Nagabhirava

Bhavin Odedara

Damian Pablo Yurzola

Rampraveen Somasundaram

Yosi Pinto

Muralitharan Jayaraman

Vijay Sivasankaran

Jayaprakash Naradasi

Tal Heller

Arun Thandapani

Jayanth Mysore Thimmaiah

Yong Peng

Yigal Eli

Srikanth Bojja

Shajith Musaliar Sirajudeen

Anand Sharma

Talal Ahwal

Arjun Hary

Anil Kumar Thadi Suryaprakash

Ajay Dhingra

Tucker Dean Berckmann

Oren Shtrasberg

A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

Tuning circuitry and operations for non-source-synchronous systems

A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.

Addressing, interleave, wear leveling, and initialization schemes for different chip enables and memory arrays of different types

A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.

Low voltage detection and initialization for non-volatile memory systems

Systems and methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.

NAND flash word line management using multiple fragment pools

Systems and methods for sequentially writing data to a memory device such as a universal serial bus (USB) memory device are disclosed. A system controller of a memory device including a first die and a second die, each of the first die and the second die including a plurality of pages, writes a first portion of a set of data to a lower page of a second die. The system controller then writes a second portion of the set of data to an upper page of the second die after writing the first portion of the set of data to the lower page of the second die.

Systems and methods for implementing a programming sequence to enhance die interleave

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Bengaluru, India

Krishnamurthy Dhakshinamurthy