Intel Corporation

Krishnakanth Venkata Sistla

Ankush Varma

Efraim Rotem

Vivek Garg

Yen-Cheng Liu

Ian M Steiner

Jeremy J Shrall

Martin Rowland

Avinash N Ananthakrishnan

Eliezer Weissmann

Stephen H Gunther

Andrew D Henroid

Ganapati Srinivasa

Vasudevan Srinivasan

Nikhil Gupta

Alexander Gendler

Guy M Therien

Anil Aggarwal

Matthew M Bace

Eugene Gorbatov

Nir Rosenzweig

Paul S Diefenbaugh

Alon Naveh

Dean A Mulla

Ashish V Choubal

Corey D Gough

Jeffrey D Gilbert

Robert E Gough

Chris MacNamara

Eric J DeHaemer

Jonathan M Eastep

Jeffrey D Chamberlain

Dorit Shapira

Jason W Brandt

John Joseph Browne

Dheeraj R Subbareddy

James G Hermerding, Ii

Gerald S Pasdast

George Zacharias Chrysos

Vedaraman Geetha

Nagasubramanian Gurumoorthy

Venkatesh Ramamurthy

Mahesh K Kumashikar

Federico Ardanaz

William R Halleck

Guy G Sotomayor

Zhong-Ning George Cai

Nevine Nassif

Barnes Cooper

Ryan Donovan Wells

David W Browning

Hang T Nguyen

Devadatta V Bodas

Tessil Thomas

Tod F Schiff

Neil W Songer

Sandeep Ahuja

Shaun M Conrad

James Steven Burns

Brian J Griffith

Robin A Steinbrecher

Xiuting C Man

Anand K Enamandram

Stefan Rusu

Robert G Blankenship

Andrew J Herdrich

Nadav Shulman

Inder M Sodhi

Jorge Pedro Rodriguez

Rakesh Kumar

Phani Kumar Kandula

Anupama Suryanarayanan

Michael A Rothman

Mohan J Kumar

Wei P Chen

Min Huang

Kristoffer Fleming

Russell Jerome Fenger

Eric DiStefano

Michael Mishaeli

Kai Cheng

Sarathy Jayakumar

Tsvika Kurts

Mark Doran

Viktor D Vogman

Ramamurthy Krithivas

Ofer Levy

Jose Andy Vargas

Richard J Greco

Larisa Novakovsky

Reid James Riedlinger

Alexander Lyakhov

Ernest Knoll

Neelam Chandwani

Edward R Stanford

Esfir Natanzon

Arvind Raman

Eswaramoorthi Nallusamy

Bryan L Spry

Geeyarpuram N Santhanakrishnan

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Current control for a multicore processor

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

Power management based on real time platform power sensing

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Multiple dies hardware processors and methods

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

Apparatus and method for dynamic control of microprocessor configuration

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

Dynamically updating logical identifiers of cores of a processor

In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

Apparatus and method to provide a thermal parameter report for a multi-chip package

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

An apparatus is provided which comprises: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.

Adaptive parameterization for maximum current protection

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

Growing community of inventors

Beaverton, OR, United States of America

Krishnakanth Venkata Sistla