Intel Corporation

Krishna Vasanth Valavala

Chandra Mohan Jha

Kelly P Lofgreen

Ravindranath Vithal Mahajan

Omkar G Karhade

Andrew Paul Collins

Weihua Tang

Chandra-Mohan Jha

An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

Integrated circuit package with flipped high bandwidth memory device

Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.

Package architecture including thermoelectric cooler structures

An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.

Annular silicon-embedded thermoelectric cooling devices for localized on-die thermal management

Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

Solid state thermoelectric cooler in silicon backend layers for fast cooling in turbo scenarios

An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.

Bump integrated thermoelectric cooler

Embodiments herein relate to systems, apparatuses, processing, and techniques related to a first heat-conducting plate to be thermally coupled to a first heat source, a thermoelectric cooler (TEC) thermally coupled to the first plate, a second heat-conducting plate thermally coupled to the TEC and to be thermally coupled to a second heat source where the TEC is to at least partially thermally isolate the first plate from the second plate to reduce heat transfer from the first plate to the second plate.

Growing community of inventors

Chandler, AZ, United States of America

Krishna Vasanth Valavala