Semtech Corporation

Mindspeed Technologies, Inc.

Raytheon Company

Krishna Shivaram

Craig A Hornbuckle

Sandeep Louis D'Souza

Kashif A Ahmed

Daniel Draper

Eric Vandel

Hehong Zou

Phung N Phan

Bronson Riley Edralin

Rodrigo Cuba

Craig Allison Hornbuckle

A capacitive sensor and capacitive sensing method including driver device having first input configured to receive clock signal, second input configured to receive charging voltage, third input configured to receive common-mode voltage, and output; first capacitor configured to be sensed, having first terminal connected to output of driver device and second terminal; and receiver device having first input configured to receive clock signal, second input connected to second terminal of first capacitor, and third input configured to receive the common mode voltage, wherein the receiver includes a temperature-compensated analog-to-digital converter (ADC), wherein the temperature-compensated ADC includes a voltage reference generator, and wherein the voltage reference generator includes a comparator, a first p-channel Metal Oxide Semiconductor (MOS) transistor, a second p-channel MOS transistor, a third p-channel MOS transistor a first variable resistor, a second variable resistor, a third variable resistor, a fourth variable resistor, a first diode, and a second diode.

Low power capacitor sensor array

An apparatus includes a current-based temperature compensation circuit having a reference buffer, a biasing current mirror, and a controller. The reference buffer is configured to receive a biasing reference voltage at a voltage input terminal and replicate the biasing reference voltage to first and second buffer terminals. At least one of the first and second buffer terminals is configured to be electrically connected to at least one gate terminal of an analog complementary metal oxide semiconductor (CMOS) physically unclonable function (PUF) cell. The biasing current mirror is configured to receive a reference current at a current input terminal and replicate the reference current to the first buffer terminal. The controller is configured to compensate an output of the CMOS PUF cell for temperature variation based on a weighted sum of a bandgap current, a current proportional to absolute temperature, and a current complementary to absolute temperature.

Temperature compensation of analog CMOS physically unclonable function for yield enhancement

A clock synchronization circuit has a clock sync detector. A first variable delay circuit is coupled to a first input of the clock sync detector. A controller is coupled to a digital output of the clock sync detector and a control input of the first variable delay circuit. A first clock signal is coupled to the first variable delay circuit. A second clock signal is coupled to a second input of the clock sync detector. The clock sync detector includes a first flip-flop and a first delay element coupled between the first variable delay circuit and a data input of the first flip-flop. A second variable delay circuit is coupled to a second input of the clock sync detector. A multiplexer is coupled between the first variable delay circuit and the first input of the clock sync detector. An offset compensation calibrates the clock sync detector.

Semiconductor device and method for accurate clock domain synchronization over a wide frequency range

A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength.

Semiconductor device and method of cascading matched frequency window tuned LC tank buffers

Examples are provided for time-interleaved analog-to-digital conversion with redundancy. The redundancy may include high-order and nested redundancies. An apparatus may include multiple analog-to-digital converter (ADC) blocks coupled to one another to form a time-interleaved ADC. Each ADC block may include multiple ADC slices, wherein a count of the ADC blocks is M and some of the ADC slices may be redundant slices. A clock circuit may be configured to provide multiple clock signals. A portion N of M ADC blocks may be configured to be active, in a normal mode of operation, where N and M are integer numbers and N is smaller than M. A remaining portion of the M ADC blocks may be redundant ADC blocks, one or more of which may be selectively active, in a healing mode of operation, and be swapped for one or more failed ADC blocks using the plurality of clock signals.

High-order and nested redundancies in time-interleaved ADCs

Examples are provided for a time-interleaved analog-to-digital converter (ADC) with built-in self-healing. The ADC may include multiple ADC slices. Each ADC slice may be configured to operate in one of a normal or a healing mode of operation. In the normal mode of operation, each ADC slice may convert an input analog signal to a single digital output signal in response to a clock signal associated with the ADC slice. In the healing mode of operation, each ADC slice may be operable to convert the input analog signal to two or more digital output signals in response to two or more clock signals. One or more of the digital output signals may replace one or more output signals of failed ADC slices. A first clock signal may be associated with the ADC slice. A second clock signal may be associated with another ADC slice of the plurality of ADC slices.

Built-in self-healing without added physical redundancy in time-interleaved ADCs

The invention relates to amplifiers and in particular, to a transimpedance amplifier for high rate applications. Disclosed is a two stage transimpedance amplifier having a first stage comprising an amplifier and a load and a second stage comprising an amplifier and a resistor. Negative feedback is provided through a feedback resistor. Only two voltage conversions occur which reduces phase distortion, as compared to three stage transimpedance amplifiers which perform 3 voltage conversions.

High sensitivity two-stage amplifier

Various amplifier configurations having increased bandwidth, linearity, dynamic range, and less distortion are shown and disclosed. To increase bandwidth in a transimpedance amplifier, a replica circuit is created to replicate a degeneration resistance, or the resistance or value that relates to a feedback resistance. From the replica circuit, the replicated values are mirrored and processed to control a FET switch which modifies a degeneration resistance. The FET switch control signal is related to the feedback resistance and modifies the degeneration resistance to thereby maintain the product of the feedback resistance and the degeneration resistance as a constant. In another embodiment, a second switch controlled by an automatic gain control signal is established between a first stage amplifier and a second stage amplifier to improve dynamic range and bandwidth without degrading other amplifier specifications.

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Torrance, CA, United States of America

Krishna Shivaram