Advanced Micro Devices Corporation

Ati Technologies Ulc

Krishna Sai Bernucho

Alexander J Branover

Andrew William Lueck

Samuel D Naffziger

Maurice B Steinman

Ronald Perez

Amitabh Mehra

Paul Blinzer

Steven Frederick Liepe

Walter G Fry

Sonu Arora

Michael J Austin

Paul Edward Kitchin

Sriram Sambamurthy

Aaron Joseph Grenat

Francisco Leonel Duran

Ming L So

Ali Ibrahim

Gary H Simpson

Christopher Eric Tressler

Ashwin Chincholi

Umair B Cheema

Mom-Eng Ng

Dan P Shimizu

Robert A Hershberger

Laura M Smith

Sho-Chien Kang

Joseph P Shannon

Xiaogang Zheng

Christopher E Tressler

A computing device includes a processor having a plurality of cores, a core translation component, and a core assignment component. The core translation component provides a set of registers, one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

Pseudo-random logical to physical core assignment at boot for age averaging

A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.

Calibrating power supply voltages using reference measurements from code loop executions

A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

Method and apparatus for transitioning a system to an active disconnect state

Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory. The processor device then configures the initial contexts one or more processor cores using the core state information maintained by the volatile memory during the low-power state and accessed via the configured memory controller, and the one or more processor cores completes the boot process by executing resume boot code maintained by the volatile memory during the low-power state and accessed via the configured memory controller, rather than accessing boot code from a non-volatile memory.

Reintialization of a processing system from volatile memory upon resuming from a low-power state

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Austin, TX, United States of America

Krishna Sai Bernucho