Advanced Micro Devices Corporation

Texas Instruments Corporation

Krishna Reddy Mudimela Venkata

Prasant Kumar Vallur

Ramon Mangaser

Srikanth Reddy Gruddanti

Pradeep Jayaraman

Sankar Prasad Debnath

Sneha Shetty

David H Mcintyre

Gerald Robert Talbot

Dean E Gonzales

Michael J Tresidder

Oikwan Tsang

A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

Clock gating using a cascaded clock gating control signal

A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.

Dual phase clock distribution from a single source in a die-to-die interface

A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Skew matching in a die-to-die interface

A circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal.

Voltage level shifter

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Bengaluru, India

Krishna Reddy Mudimela Venkata